make memory encryption bit an upper limit for physical address bits

[Freax13]

Ensure that no bit above the C-bit/S-bit is set:

• TDX already requires this: "GPA bits higher than the SHARED bit are considered reserved and must be 0. Address translation with any of the reserved bits set to 1 cause a #PF with PFEC (Page Fault Error Code) RSVD bit set." (Architecture Specification: Intel® Trust Domain Extensions (Intel® TDX) Module, 13.11.1. GPAW-Relate EPT Violations).
• AMD CPUs don't have the same restriction, however in practice, the C-bit is always the upmost supported physical adddress bit. Client parts and server parts up until Rome support 48 physical address bits and use bit 47 as the C-bit. Server parts starting with Milan support 52 physical address bits and always use bit 51 as the C-bit. Thinking about this, this makes sense: If the CPU allowed bits higher than the C-bit to be used for address bits, this would fragment the physical address space and make large parts of it effectively unusable.

[Freax13]

The failing CI jobs will be addressed by #604.