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perf(VMProm): refactor the TLB - #273
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tperami
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The BBM checker has a bug where it will miss a conflict between a global page entry and an ASID-specific block entry that overlap. I'm writing this to record it because I'm not sure if we have a test for that. |
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Otherwise, @febyeji it's ready for review |
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LGTM. This can be merged after the tests are uncommented.
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This is a quite big refactor, however more than half the diff in VMPromising.v is just moving the TState after the TLB. The main gist is that now the TLB is part of the TState for performance, although it can be recomputed from the register and memory state at any point. The TLB also contains information about all timestamps instead of just one. The 3 BBM mode are gone, and the BBM checker is either on or off. Entries that a not-present can't be in conflict. If that is important for proofs, the proof should have a precondition that all page table are present.
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This is a quite big refactor, however more than half the diff in
VMPromising.v is just moving the TState after the TLB.
The main gist is that now the TLB is part of the TState for performance,
although it can be recomputed from the register and memory state at any point.
The TLB also contains information about all timestamps instead of just
one.
The 3 BBM mode are gone, and the BBM checker is either on or off.
Entries that a not-present can't be in conflict. If that is important
for proofs, the proof should have a precondition that all page table are
present.
This PR is part of a stack containing 4 PRs:
main