[graph_trainer] Overlap HybridEP and paging across combined PP graphs

[sanketpurandare]

AI-Generated Details

Prepared with Codex from the author's GraphPP multiplexing design.

Interleaved1F1BCombined uses the companion native PyTorch schedule:
pytorch/pytorch#201439

Multiplex independent forward/backward graphs without EP token chunking or
capacity division. Explicit source annotations preserve ownership and input/
output ABI. Reuse the earlier eager scheduler's native request/input validator,
tensor/mutation dependencies and paging queue contracts. Existing pipeline code
retains receives, unshards, sends, gradient accumulation and callbacks. The
earlier pager owns calibration/live-prefix handling, the no-AC policy and
source-aware paging dependencies; this PR consumes them unchanged.

Each communication launch, including paging, now yields to ready compute in
the complementary source. The shared early-launch/late-wait scheduler now
prefers launch-enabling computations over unrelated wgrad, without another
scheduler or timing heuristic. Source-aware paging order allows F/B interleaving while the
single high-priority page stream serializes freelist updates. High-priority EP
and page streams and their environment-controlled launch budgets come from the
earlier owning PRs. Compute is not SM-bounded. No new scheduling framework,
copied kernel, capacity division or paging-buffer change is added.

Native varlen Flash selects FA4 on Blackwell. Combined and DualPipeV coverage
uses real control/overlap/paging paths. DualPipeV retains its native two-stage-
per-rank V mapping, full backward for combined actions and separate dI/dW for
bubbles. dI keeps required live-ins until dW produces parameter gradients.
There is no copied schedule or patched acceptance path.

Whole-step CUDA capture includes all microbatches' distinct routing state.
Native experimental graph_capture_record_stream_reuse releases storage only
after graph dependencies prove asynchronous uses joined; keep it equal in both
arms. It does not replace ownership, annotations or stream waits. The obsolete
future-EP-composition limitation is removed. DeepEP and full-graph Inductor are
outside scope; the companion PyTorch draft is unchanged by this update.

Verification

The native eager MoE graph regression passed: the final chunk0 input-gradient
combine issues before both independent expert weight-gradient GEMMs. It uses
the production tracer and mandatory graph normalization, not patched metadata.
The launch-ancestor preference is derived once from the existing annotated DAG;
no kernel, arithmetic, capacity, compute-SM policy or extra scheduler changes.

Full-CUDA SPMD no-AC, combined PP no-AC and DualPipeV paging numerical comparisons
and the packaged-runtime 16B profile must pass on this exact revision before
publication. Earlier native API/paging checks passed non-default budgets,
invalid settings, captured node priorities, grids, lifetimes and exact replay
bytes. New scale speedup or near-complete hiding is not claimed by this update.

Original source bdee7476 completed 16B 64-GPU PP runs: PP=2, DP=EP=32, TP=1,
four stages per rank, 64 microbatches of 4 sequences, length 1024, no AC/SAC,
FA4, paging in both arms and full CUDA. Balanced 1x measured 1,239,218 ->
1,295,503 configured tokens/s (1.045x); real-routing balanced 8x measured
605,265 -> 660,787 (1.092x). All seven raw paired loss/norm samples matched.
Sixty steps, throughput 11-50, profiler 59-60, snapshot 60 and identical
allocator/history settings were used.

Those original traces retain substantial exposed EP/page work: forced
EP 1557.59 ms/page 304.35 ms and real EP 2650.64 ms/page 293.34 ms, rank 0 over
two full replays. They do not meet the author's 1.2x target or prove near-complete hiding.
Improved overlap-only 32/64-GPU measurements remain pending and are not inferred
from pass logs, stream IDs or older gains. Owned lint/doc hooks passed; the
untouched video typing baseline remains outside scope.