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Cannot verify a design with sec that lec says is equivalent

Status: Open.

#192 In keplertech/kepler-formal;

· jeffng-or opened on Aug 6, 2026

Encountering conflicting sequential clocks on memory IP

Status: Open.

#191 In keplertech/kepler-formal;

· jeffng-or opened on Aug 6, 2026

SEC structural loop breaking?

Status: Open.

#189 In keplertech/kepler-formal;

· jeffng-or opened on Aug 4, 2026

ModuleNotFoundError when trying to load in py_tech_files

Status: Open.

#178 In keplertech/kepler-formal;

· jeffng-or opened on Jul 30, 2026

No option to specify verilog top module?

Status: Open.

#174 In keplertech/kepler-formal;

· jeffng-or opened on Jul 28, 2026

Cross-engine gate-vs-gate equivalence (two synthesis tools, same RTL): supported use-case? LEC or SEC?

Status: Open.

#167 In keplertech/kepler-formal;

· oharboe opened on Jul 17, 2026

Feature request - Publish kepler-formal on bazel bcr

Status: Open.

#165 In keplertech/kepler-formal;

· oharboe opened on Jul 16, 2026