GFNI with XMM registers over 3 times as fast as SSE

[jeffareid]

I created a test set of gf_#vect_dot_prod_gfni.asm files.
On my laptop, for RS(20,14), m=20, k=14, p=6, 48KB per row, SSE: 5.5 GB / sec, GFNI: 20.2 GB / sec.

@pablodelara - I realize that this only affects a small number of processors (or maybe just the one you previously mentioned), but it wasn't that difficult to create these files. I did not create the ...mad... files.

[jeffareid]

@pablodelara - link to directory that includes gf_#vect_dot_prod_gfni.asm files. I did this back in October, before the padding of g_tbls, so the code assumes 8 bytes per entry. I use my web-site since it keeps the file dates, although you would need to use wget to preserve the time-stamps with a download.

https://rcgldr.net/ers/

[pablodelara]

Thanks @jeffareid. Given this is your code, you should create a PR with it (this will go into next release though).

[jeffareid]

@pablodelara - I'd want to do more testing to make sure there are no issues. Should the file and function names be changed from ...prod_gfni to ...prod_avx_gfni? I'd also need to change the code to handle the padding to 32 bytes.

[pablodelara]

Sure. But all functions have the _avx2_gfni/_avx512_gfni already, so it would be a matter of adding _sse_gfni functions.

[jeffareid]

@pablodelara - Looking at the current SSE code which I modded to create the GFNI code, unlike the other variations, there is no masking of read | write for the last chunk of < 16 bytes. Maybe the masking didn't exist at the time of SSE?

[jeffareid]

@pablodelara - from another issue: "there are processors that with SSE+GFNI available ..."

https://www.intel.com/content/www/us/en/products/sku/134793/intel-atom-processor-p5362-27m-cache-2-2ghz/specifications.html)

[pablodelara]

@pablodelara - Looking at the current SSE code which I modded to create the GFNI code, unlike the other variations, there is no masking of read | write for the last chunk of < 16 bytes. Maybe the masking didn't exist at the time of SSE?

Do you mean masked loads/stores with predication masks k1, k2...? That was introduced in AVX512.

[pablodelara]

@pablodelara - from another issue: "there are processors that with SSE+GFNI available ..."

https://www.intel.com/content/www/us/en/products/sku/134793/intel-atom-processor-p5362-27m-cache-2-2ghz/specifications.html)

Correct

[jeffareid]

@pablodelara - masked load | stores | AVX512, that explains the SSE code.

Finding an Atom processor with GFNI would be difficult. I did a search, and the old cheap netbooks predate GFNI. I've seen some boards that could have Atom | GFNI, but creating a working system using one of those boards would be expensive. It appears that these processors were used for a while on servers.

I'm wondering if something like a P5362 processor would have masked load|store, despite not having AVX512, but I don't see a reasonably cheap way to get a system to test it.

[pablodelara]

They are Atom servers with CPU codename Snow Ridge (https://www.intel.com/content/www/us/en/products/sku/134793/intel-atom-processor-p5362-27m-cache-2-2ghz/specifications.html).
And the answer to your questions is no. Masked load/store instructions were introduced with AVX512.

[jeffareid]

@pablodelara - I uploaded sse gfni assembly code for ISA-L to my repository. I haven't created mad versions yet. Waiting to see if there is any interest.

https://github.com/jeffareid/ssegfni