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[ciq-6.12.y] Multiple patches tested (9 commits)#1320

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[ciq-6.12.y] Multiple patches tested (9 commits)#1320
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Summary

This PR has been automatically created after successful completion of all CI stages.

Commit Message(s)

arm64: cputype: Add Cortex-A720AE definitions

cve-pre CVE-2025-10263
commit-author Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
commit f38c2c3e572ce0ce5c01de0358ed70328e0cb5af

arm64: cputype: Add C1-Pro definitions

cve-pre CVE-2025-10263
commit-author Catalin Marinas <catalin.marinas@arm.com>
commit 2c99561016c591f4c3d5ad7d22a61b8726e79735

arm64: cputype: Add C1-Ultra definitions

cve-pre CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit -
commit-source https://lore.kernel.org/all/20260609101203.1512409-2-mark.rutland@arm.com/

arm64: cputype: Add C1-Premium definitions

cve-pre CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit -
commit-source https://lore.kernel.org/all/20260609101203.1512409-3-mark.rutland@arm.com/

arm64: errata: Mitigate TLBI errata on various Arm CPUs

cve CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit -
commit-source https://lore.kernel.org/all/20260609101203.1512409-4-mark.rutland@arm.com/
upstream-diff silicon-errata.rst required manual conflict resolution due to
  condensed table formatting in our branch vs multi-line entries upstream.
  Content is identical; C1-Pro errata row not present as its workaround
  (DVMSync) is not backported.

arm64: cputype: Add NVIDIA Olympus definitions

cve-pre CVE-2025-10263
commit-author Shanker Donthineni <sdonthineni@nvidia.com>
commit e185c8a0d84236d14af61faff8147c953a878a77

arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU

cve CVE-2025-10263
commit-author Shanker Donthineni <sdonthineni@nvidia.com>
commit -
commit-source-sha ec7216f92e4ebd485b1c6dc6aa3f6064b71a5768
commit-source arm64

arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU

cve CVE-2025-10263
commit-author Will Deacon <will@kernel.org>
commit -
commit-source-sha 1940e70a8144bf75e6df26bf6f600862ea7f7ea1
commit-source arm64

[CIQ] ciq_kernel-6.12.93-2 - updated spec

Test Results

✅ Build Stage

Architecture Build Time Total Time
x86_64 34m 0s 34m 46s
aarch64 20m 42s 21m 18s

✅ Boot Verification

✅ Kernel Selftests

Architecture Passed Failed Compared Against Status
x86_64 322 71 ciq-6.12.y ✅ No regressions
aarch64 267 65 ciq-6.12.y ✅ No regressions

✅ LTP Results

Architecture Passed Failed Compared Against Status
x86_64 1482 81 ciq-6.12.y ✅ No regressions
aarch64 1455 82 ciq-6.12.y ✅ No regressions

🤖 This PR was automatically generated by GitHub Actions
Run ID: 27346514981

@bmastbergen
arm64: cputype: Add Cortex-A720AE definitions
5f45579 
cve-pre CVE-2025-10263
commit-author Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
commit f38c2c3

Add cputype definitions for Cortex-A720AE. These will be used for errata
detection in subsequent patches.

These values can be found in the Cortex-A720AE TRM:

https://developer.arm.com/documentation/102828/0001/

... in Table A-187

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit f38c2c3)
Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
@bmastbergen
arm64: cputype: Add C1-Pro definitions
bc04079 
cve-pre CVE-2025-10263
commit-author Catalin Marinas <catalin.marinas@arm.com>
commit 2c99561

Add cputype definitions for C1-Pro. These will be used for errata
detection in subsequent patches.

These values can be found in "Table A-303: MIDR_EL1 bit descriptions" in
issue 07 of the C1-Pro TRM:

  https://documentation-service.arm.com/static/6930126730f8f55a656570af

Acked-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Reviewed-by: Will Deacon <will@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 2c99561)
Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
@bmastbergen
arm64: cputype: Add C1-Ultra definitions
80bc8e5 
cve-pre CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit -
commit-source https://lore.kernel.org/all/20260609101203.1512409-2-mark.rutland@arm.com/

Add cputype definitions for C1-Ultra. These will be used for errata
detection in subsequent patches.

These values can be found in the C1-Ultra TRM:

  https://developer.arm.com/documentation/108014/0100/

... in section A.5.1 ("MIDR_EL1, Main ID Register").

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
@bmastbergen
arm64: cputype: Add C1-Premium definitions
e8af69e 
cve-pre CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit -
commit-source https://lore.kernel.org/all/20260609101203.1512409-3-mark.rutland@arm.com/

Add cputype definitions for C1-Premium. These will be used for errata
detection in subsequent patches.

These values can be found in the C1-Premium TRM:

  https://developer.arm.com/documentation/109416/0100/

... in section A.5.1 ("MIDR_EL1, Main ID Register").

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
@bmastbergen
arm64: errata: Mitigate TLBI errata on various Arm CPUs
863a1f9 
cve CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit -
commit-source https://lore.kernel.org/all/20260609101203.1512409-4-mark.rutland@arm.com/
upstream-diff silicon-errata.rst required manual conflict resolution due to
  condensed table formatting in our branch vs multi-line entries upstream.
  Content is identical; C1-Pro errata row not present as its workaround
  (DVMSync) is not backported.

A number of CPUs developed by Arm suffer from errata whereby a broadcast
TLBI;DSB sequence may complete before the global observation of writes
which are translated by an affected TLB entry.

These errata ONLY affect the completion of memory accesses which have
been translated by an invalidated TLB entry, and these errata DO NOT
affect the actual invalidation of TLB entries. TLB entries are removed
correctly.

This issue has been assigned CVE ID CVE-2025-10263.

To mitigate this issue, Arm recommends that software follows any
affected TLBI;DSB sequence with an additional TLBI;DSB, which will
ensure that all memory write effects affected by the first TLBI have
been globally observed. The additional TLBI can use any operation that
is broadcast to affected CPUs, and the additional DSB can use any option
that is sufficient to complete the additional TLBI.

The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate
the issue. Enable this workaround for affected CPUs, and update the
silicon errata documentation accordingly.

Note that due to the manner in which Arm develops IP and tracks errata,
some CPUs share a common erratum number.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
@bmastbergen
arm64: cputype: Add NVIDIA Olympus definitions
c65e6ea 
cve-pre CVE-2025-10263
commit-author Shanker Donthineni <sdonthineni@nvidia.com>
commit e185c8a

Add cpu part and model macro definitions for NVIDIA Olympus core.

Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com>
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit e185c8a)
Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
@ciq-kernel-automation ciq-kernel-automation Bot added the created-by-kernelci Tag PRs that were automatically created when a user branch was pushed to the repo (kernelCI) label Jun 10, 2026
PlaidCat
PlaidCat approved these changes Jun 10, 2026
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:shipit:

@bmastbergen
arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU
61e07c1 
cve CVE-2025-10263
commit-author Shanker Donthineni <sdonthineni@nvidia.com>
commit -
commit-source-sha ec7216f92e4ebd485b1c6dc6aa3f6064b71a5768
commit-source arm64

NVIDIA Olympus cores are affected by the TLBI completion issue tracked as
CVE-2025-10263. The existing ARM64_ERRATUM_4118414 handling already uses
ARM64_WORKAROUND_REPEAT_TLBI to issue an additional broadcast TLBI;DSB
sequence and ensure affected memory write effects are globally observed.

Add MIDR_NVIDIA_OLYMPUS to the repeat-TLBI match list so the same
mitigation is enabled on affected Olympus systems. Also document the
NVIDIA Olympus erratum in the arm64 silicon errata table and list it in
the Kconfig help text.

	Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com>
	Cc: Catalin Marinas <catalin.marinas@arm.com>
	Cc: Will Deacon <will@kernel.org>
	Cc: Mark Rutland <mark.rutland@arm.com>
	Acked-by: Mark Rutland <mark.rutland@arm.com>
	Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit ec7216f92e4ebd485b1c6dc6aa3f6064b71a5768)
	Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
@bmastbergen
arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU
e773768 
cve CVE-2025-10263
commit-author Will Deacon <will@kernel.org>
commit -
commit-source-sha 1940e70a8144bf75e6df26bf6f600862ea7f7ea1
commit-source arm64

Commit fb091ff ("arm64: Subscribe Microsoft Azure Cobalt 100 to ARM
Neoverse N2 errata") states that Microsoft Azure Cobalt 100 CPU "is a
Microsoft implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and
therefore suffers from all the same errata.".

So enable the workaround for the latest broadcast TLB invalidation bug
on these parts.

	Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 1940e70a8144bf75e6df26bf6f600862ea7f7ea1)
	Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
@bmastbergen
[CIQ] ciq_kernel-6.12.93-2 - updated spec
733760a
@bmastbergen bmastbergen force-pushed the {bmastbergen}_ciq-6.12.y branch from 0411642 to 733760a Compare June 11, 2026 12:23
@bmastbergen bmastbergen requested a review from a team June 11, 2026 15:12
@roxanan1996

roxanan1996 commented Jun 11, 2026

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CONFIG_ARM64_ERRATUM_4118414 should be added in configs. I lost track if you do that later, or it should be addressed here.
But otherwise, it looks correct.

@bmastbergen bmastbergen merged commit f1c4fd8 into ciq-6.12.y Jun 11, 2026
9 checks passed
@bmastbergen bmastbergen deleted the {bmastbergen}_ciq-6.12.y branch June 11, 2026 19:23
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