CUDA TP with exactly two GPUs is classified single-tier and OOMs on GPU 0

[gitjburns]

Environment:
2x RTX PRO 6000 Blackwell (96 GB, sm_120), driver 595.91.07 (open kernel module), CUDA 13.3, DeepSeek-V4-Flash MXFP4 GGUF (145.26 GiB).

Command:
./ds4 --cuda --cuda-tensor-parallel --gpu-devices 0,1 --ctx 10000

Symptom:
only dev=0 initializes; startup copies the whole model into GPU 0 and dies with CUDA model arena alloc failed ... out of memory at ~56 GiB, then cuda failed to prepare optional model cache.

Root cause:
engine_classify_multi_tier derives multi_tier from layer spread across placement entries. CUDA TP places partner tiers by half index, never in placement[]. With two GPUs there is one stage, every entry is tier 0, and the engine takes the single-tier path: one device, no per-device caches, no partner. The single-tier startup walk then needs the whole mmap host-registered (cudaHostRegisterReadOnly), which the open kernel module reports unsupported (HostRegisterReadOnlySupported=0), so it falls into the device arena and fills GPU 0 until OOM. Four- and eight-GPU layouts never hit this because multiple stages already spread the layers.

Fix:
treat a requested CUDA decode TP layout as multi-tier.

--- a/ds4.c
+++ b/ds4.c
@@ -62278,6 +62278,12 @@ static int engine_classify_multi_tier(...)
+    /* CUDA decode TP pairs every layer-home tier with a partner tier that
+     * never appears in placement[] (partners are derived from the half
+     * index). A single-stage pair therefore looks single-tier above, yet
+     * its partner is always a second device that must take the multi-tier
+     * path (per-device caches, partner scratch). */
+    if (!multi_tier && engine_cuda_tp_decode_requested(e)) multi_tier = 1;
     e->multi_tier = multi_tier;

Verified:
same command now initializes both devices, validates peer access (DIRECT), installs 76.47 GiB on tier 0 and 75.48 GiB on tier 1 (half-resident experts, replicated dense, 2-way output shard), and answers a prompt at 69 tok/s generation. Built with make cuda CUDA_ARCH=sm_120.