💡 RTL Design • Digital Systems • Data Structures & Algorithms

I am an Electronics and Communication Engineering undergraduate specializing in VLSI Design and Digital Systems. I enjoy translating complex algorithms into efficient hardware architectures and implementing synthesizable RTL designs using Verilog. Alongside hardware design, I actively strengthen my problem-solving skills through competitive programming and Data Structures & Algorithms in Java.

• 🔭 Working on: RTL Design & FPGA Implementation
• 🧠 Currently learning: Dynamic Programming (DSA in Java)
• 🛠️ Exploring: ASIC Design Flow & Digital Verification
• ⚡ Interested in: Microarchitecture, Timing Analysis & High-Performance Design

• Verilog (RTL Design & Simulation)
• Digital Logic Design
• Finite State Machines (FSM)
• FPGA Fundamentals
• CMOS Theory
• Basic ASIC Design Flow

• Java
• Object-Oriented Programming (OOP)
• Python (Basics)
• C (Basics)

• Dynamic Programming (Optimization Problems)
• RTL Optimization & Clean Coding in Verilog
• Synthesis & Timing Concepts
• Strengthening Digital Design Fundamentals

• 🔗 LinkedIn: Puttamraju Krishna Hridayesh Kumar

To work in semiconductor design and contribute to building efficient, scalable, and high-performance digital systems.