Include multiplication reverse engineering?

[ghost]

Hello,

A while ago, I reverse engineered how multiplication inside of the MIPS CPU core works. This was done by issuing carefully timed writes to the LO/HI registers after starting the operation. I noticed that the ranges used to determine timing were different than what Martin had in his docs. I attempted to contact him directly but it was a giant pain, and I gave up on it. Since this should be easier, I'm just making it known that this exists and is 100% verified on my SCPH-7501 and SCPH-5501 consoles.

If there's interest, I can include a write-up of the DIV/DIVU operations as well.

[nicolasnoble]

Totally feel free to issue pull requests with your findings :)

[ghost]

Sorry for not getting back sooner. I decided to try and write an implementation with the docs I linked to and couldn't even follow my own writing! Once I have that cleaned up I'll make a PR.

[nicolasnoble]

No worries at all. Take your time, there's no rush.

[rixnobis]

The page still carries the original table. Its signed side overlaps itself: mult Med ends at FFFFF801h while Fast starts at FFFFF800h, and Slow ends at FFF00001h while Med starts at FFF00000h. I'll time mult with rs at FFFFF7FFh, FFFFF800h, FFFFF801h, FFEFFFFFh, FFF00000h and FFF00001h on a console and fix the table from those numbers. The DIV notes are still welcome as a PR.

[rixnobis]

Timed on hardware and fixed in #133. On the signed side FFFFF7FFh is Med and FFEFFFFFh is Slow, so mult is Fast for FFFFF800h..FFFFFFFFh, Med for FFF00000h..FFFFF7FFh and Slow for 80000000h..FFEFFFFFh. multu and the 6/9/13 counts were already right. Only rs picks the class: the same values in rt with rs=5 all take the Fast time. The probe is tests/mult-timing in pcsx-redux/nugget.