From ec2bfe6ea02064fad4e7d484d903114483e50027 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 29 Aug 2025 12:49:33 +0100 Subject: [PATCH 001/126] dt-bindings: interrupt-controller: Add compatible for MT8163 sysirq Add compatible for MT8163 sysirq controller. Signed-off-by: Ben Grisdale --- .../bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml index 30d76692ca87b5..7079afb3f36d59 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml @@ -36,6 +36,7 @@ properties: - mediatek,mt7629-sysirq - mediatek,mt8127-sysirq - mediatek,mt8135-sysirq + - mediatek,mt8163-sysirq - mediatek,mt8173-sysirq - mediatek,mt8183-sysirq - mediatek,mt8365-sysirq From fe0b6df11b5295a55b81940f173623e005c6c772 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Tue, 9 Sep 2025 15:46:05 +0100 Subject: [PATCH 002/126] dt-bindings: timer: Add compatible for MT8163 timer Add a device tree binding for the systimer (GPT) on the MT8163 SoC. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/timer/mediatek,timer.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml index 337580dc77d82b..fcf4303e1426c4 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml +++ b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt7623-timer - mediatek,mt8127-timer - mediatek,mt8135-timer + - mediatek,mt8163-timer - mediatek,mt8173-timer - mediatek,mt8516-timer - const: mediatek,mt6577-timer From ecacca6bacd47ebcc8078270bf1e71151f0838e4 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 29 Aug 2025 13:13:25 +0100 Subject: [PATCH 003/126] arm64: dts: mediatek: Add support for MT8163 platform Add a device tree providing basic platform support for MT8163. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 198 +++++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8163.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi new file mode 100644 index 00000000000000..c858a61ccd89ee --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&sysirq>; + compatible = "mediatek,mt8163"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + clocks { + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + arm,no-tick-in-suspend; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + timer: timer@10008000 { + compatible = "mediatek,mt8163-timer", "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x1000>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt8163-sysirq", "mediatek,mt6577-sysirq"; + reg = <0 0x10200620 0 0x20>; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + }; + + gic: interrupt-controller@10221000 { + compatible = "arm,gic-400"; + reg = <0 0x10221000 0 0x1000>, + <0 0x10222000 0 0x1000>, + <0 0x10224000 0 0x2000>, + <0 0x10226000 0 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + cci: cci@10390000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x10390000 0 0x1000>; + ranges = <0 0 0x10390000 0x10000>; + + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace-lite"; + reg = <0x1000 0x1000>; + }; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = , + , + , + , + ; + }; + }; + }; +}; From 09c13c1b5c89e287567e828ff4c12197e4863997 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 16:09:48 +0100 Subject: [PATCH 004/126] dt-bindings: clock: Add bindings for MT8163 main clock controllers Add device tree bindings for the main clock controllers on the MT8163 SoC, including apmixedsys, infracfg, pericfg and topckgen. Signed-off-by: Ben Grisdale --- .../bindings/clock/mediatek,apmixedsys.yaml | 1 + .../bindings/clock/mediatek,infracfg.yaml | 1 + .../bindings/clock/mediatek,pericfg.yaml | 1 + .../bindings/clock/mediatek,topckgen.yaml | 1 + .../clock/mediatek,mt8163-apmixedsys.h | 23 +++++ .../clock/mediatek,mt8163-infracfg.h | 80 +++++++++++++++++ .../clock/mediatek,mt8163-topckgen.h | 90 +++++++++++++++++++ .../reset/mediatek,mt8163-infracfg.h | 26 ++++++ 8 files changed, 223 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt8163-apmixedsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt8163-infracfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt8163-topckgen.h create mode 100644 include/dt-bindings/reset/mediatek,mt8163-infracfg.h diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml index 591a9e862c7d46..e09603061f160a 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml @@ -40,6 +40,7 @@ properties: - mediatek,mt6779-apmixed - mediatek,mt6795-apmixedsys - mediatek,mt7629-apmixedsys + - mediatek,mt8163-apmixedsys - mediatek,mt8167-apmixedsys - mediatek,mt8183-apmixedsys - const: syscon diff --git a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml index d1d30700d9b0e4..0ff47294b20ecd 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt7986-infracfg - mediatek,mt7988-infracfg - mediatek,mt8135-infracfg + - mediatek,mt8163-infracfg - mediatek,mt8167-infracfg - mediatek,mt8173-infracfg - mediatek,mt8183-infracfg diff --git a/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml index b98cf45efe2f63..f4f57d864fac59 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt7622-pericfg - mediatek,mt7629-pericfg - mediatek,mt8135-pericfg + - mediatek,mt8163-pericfg - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg - mediatek,mt8186-pericfg diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml index c080fb0a161819..6ac157ec389ab7 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml @@ -41,6 +41,7 @@ properties: - mediatek,mt7986-topckgen - mediatek,mt7988-mcusys - mediatek,mt7988-topckgen + - mediatek,mt8163-topckgen - mediatek,mt8167-topckgen - mediatek,mt8183-topckgen - const: syscon diff --git a/include/dt-bindings/clock/mediatek,mt8163-apmixedsys.h b/include/dt-bindings/clock/mediatek,mt8163-apmixedsys.h new file mode 100644 index 00000000000000..4636de79eb0754 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8163-apmixedsys.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_MT8163_APMIXEDSYS_H +#define _DT_BINDINGS_CLOCK_MT8163_APMIXEDSYS_H + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MMPLL 3 +#define CLK_APMIXED_MSDCPLL 4 +#define CLK_APMIXED_VENCPLL 5 +#define CLK_APMIXED_TVDPLL 6 +#define CLK_APMIXED_MPLL 7 +#define CLK_APMIXED_AUD1PLL 8 +#define CLK_APMIXED_AUD2PLL 9 +#define CLK_APMIXED_LVDSPLL 10 +#define CLK_APMIXED_SSUSB_26M 11 +#define CLK_APMIXED_ARMPLL_26M 12 +#define CLK_APMIXED_MIPI_26M 13 +#define CLK_APMIXED_REF2USB_TX 14 +#define CLK_APMIXED_NR_CLK 15 + +#endif /* _DT_BINDINGS_CLOCK_MT8163_APMIXEDSYS_H */ diff --git a/include/dt-bindings/clock/mediatek,mt8163-infracfg.h b/include/dt-bindings/clock/mediatek,mt8163-infracfg.h new file mode 100644 index 00000000000000..6c92243f1f9e5a --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8163-infracfg.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_MT8163_INFRACFG_H +#define _DT_BINDINGS_CLOCK_MT8163_INFRACFG_H + +#define CLK_INFRA_PMIC_TMR 0 +#define CLK_INFRA_PMIC_AP 1 +#define CLK_INFRA_PMIC_MD 2 +#define CLK_INFRA_PMIC_CONN 3 +#define CLK_INFRA_SCPSYS 4 +#define CLK_INFRA_SEJ 5 +#define CLK_INFRA_APXGPT 6 +#define CLK_INFRA_USB 7 +#define CLK_INFRA_ICUSB 8 +#define CLK_INFRA_GCE 9 +#define CLK_INFRA_THERM 10 +#define CLK_INFRA_I2C0 11 +#define CLK_INFRA_I2C1 12 +#define CLK_INFRA_I2C2 13 +#define CLK_INFRA_PWM_HCLK 14 +#define CLK_INFRA_PWM1 15 +#define CLK_INFRA_PWM2 16 +#define CLK_INFRA_PWM3 17 +#define CLK_INFRA_PWM 18 +#define CLK_INFRA_UART0 19 +#define CLK_INFRA_UART1 20 +#define CLK_INFRA_UART2 21 +#define CLK_INFRA_UART3 22 +#define CLK_INFRA_USB_MCU 23 +#define CLK_INFRA_NFI_ECC_66M 24 +#define CLK_INFRA_NFI_66M 25 +#define CLK_INFRA_BTIF 26 +#define CLK_INFRA_SPI 27 +#define CLK_INFRA_MSDC3 28 +#define CLK_INFRA_MSDC1 29 +#define CLK_INFRA_MSDC2 30 +#define CLK_INFRA_MSDC0 31 +#define CLK_INFRA_GCPU 32 +#define CLK_INFRA_TRNG 33 +#define CLK_INFRA_AUXADC 34 +#define CLK_INFRA_CPUM 35 +#define CLK_INFRA_IRRX 36 +#define CLK_INFRA_UFO 37 +#define CLK_INFRA_CEC 38 +#define CLK_INFRA_CEC_26M 39 +#define CLK_INFRA_NFI_BCLK 40 +#define CLK_INFRA_NFI_ECC 41 +#define CLK_INFRA_AP_DMA 42 +#define CLK_INFRA_XIU 43 +#define CLK_INFRA_DEVICE_APC 44 +#define CLK_INFRA_XIU2AHB 45 +#define CLK_INFRA_L2C_SRAM 46 +#define CLK_INFRA_ETH_50M 47 +#define CLK_INFRA_DEBUGSYS 48 +#define CLK_INFRA_AUDIO 49 +#define CLK_INFRA_ETH_25M 50 +#define CLK_INFRA_NFI 51 +#define CLK_INFRA_ONFI 52 +#define CLK_INFRA_SNFI 53 +#define CLK_INFRA_ETH 54 +#define CLK_INFRA_DRAMC_F26M 55 +#define CLK_INFRA_OSC 56 +#define CLK_INFRA_OSC_D8 57 +#define CLK_INFRA_OSC_D16 58 +#define CLK_INFRA_CLK26M_D8 59 +#define CLK_INFRA_ETH_D2 60 +#define CLK_INFRA_ONFI_D2 61 +#define CLK_INFRA_UART0_SEL 62 +#define CLK_INFRA_UART1_SEL 63 +#define CLK_INFRA_UART2_SEL 64 +#define CLK_INFRA_UART3_SEL 65 +#define CLK_INFRA_SPI_SEL 66 +#define CLK_INFRA_DRAMC_SEL 67 +#define CLK_INFRA_ULPOSC_SEL 68 +#define CLK_INFRA_ETH_25M_SEL 69 +#define CLK_INFRA_NFI_SEL 70 +#define CLK_INFRA_CA53SEL 71 +#define CLK_INFRA_NR_CLK 72 + +#endif /* _DT_BINDINGS_CLOCK_MT8163_INFRACFG_H */ diff --git a/include/dt-bindings/clock/mediatek,mt8163-topckgen.h b/include/dt-bindings/clock/mediatek,mt8163-topckgen.h new file mode 100644 index 00000000000000..41f50b8acd9b8f --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8163-topckgen.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_MT8163_TOPCKGEN_H +#define _DT_BINDINGS_CLOCK_MT8163_TOPCKGEN_H + +#define CLK_TOP_DMPLL 0 +#define CLK_TOP_DSI0_LNTC_DSICK 1 +#define CLK_TOP_F26M_MEM_CKGEN_OCC 2 +#define CLK_TOP_LVDSTX_CLKDIG_CTS 3 +#define CLK_TOP_MAIN_H546M 4 +#define CLK_TOP_MAIN_H364M 5 +#define CLK_TOP_MAIN_H218P4M 6 +#define CLK_TOP_MAIN_H156M 7 +#define CLK_TOP_UNIV_624M 8 +#define CLK_TOP_UNIV_416M 9 +#define CLK_TOP_UNIV_249P6M 10 +#define CLK_TOP_UNIV_178P3M 11 +#define CLK_TOP_UNIV_48M 12 +#define CLK_TOP_CLKRTC_INT 13 +#define CLK_TOP_HDMI_CTS 14 +#define CLK_TOP_HDMI_CTS_D2 15 +#define CLK_TOP_HDMI_CTS_D3 16 +#define CLK_TOP_LVDSPLL_D2 17 +#define CLK_TOP_LVDSPLL_D4 18 +#define CLK_TOP_LVDSPLL_D8 19 +#define CLK_TOP_LVDSPLL_ETH 20 +#define CLK_TOP_MSDCPLL_D2 21 +#define CLK_TOP_MSDCPLL_D4 22 +#define CLK_TOP_SYSPLL_D2P5 23 +#define CLK_TOP_SYSPLL1_D2 24 +#define CLK_TOP_SYSPLL1_D4 25 +#define CLK_TOP_SYSPLL1_D8 26 +#define CLK_TOP_SYSPLL1_D16 27 +#define CLK_TOP_SYSPLL2_D2 28 +#define CLK_TOP_SYSPLL2_D4 29 +#define CLK_TOP_SYSPLL2_D8 30 +#define CLK_TOP_SYSPLL3_D2 31 +#define CLK_TOP_SYSPLL3_D4 32 +#define CLK_TOP_SYSPLL4_D2 33 +#define CLK_TOP_SYSPLL4_D4 34 +#define CLK_TOP_TVDPLL_D2 35 +#define CLK_TOP_TVDPLL_D4 36 +#define CLK_TOP_TVDPLL_D8 37 +#define CLK_TOP_TVDPLL_D16 38 +#define CLK_TOP_UNIVPLL_D2P5 39 +#define CLK_TOP_UNIVPLL1_D2 40 +#define CLK_TOP_UNIVPLL1_D4 41 +#define CLK_TOP_UNIVPLL2_D2 42 +#define CLK_TOP_UNIVPLL2_D4 43 +#define CLK_TOP_UNIVPLL2_D8 44 +#define CLK_TOP_UNIVPLL3_D2 45 +#define CLK_TOP_UNIVPLL3_D4 46 +#define CLK_TOP_UNIVPLL3_D8 47 +#define CLK_TOP_AXI_SEL 48 +#define CLK_TOP_MEM_SEL 49 +#define CLK_TOP_DDRPHYCFG_SEL 50 +#define CLK_TOP_MM_SEL 51 +#define CLK_TOP_PWM_SEL 52 +#define CLK_TOP_VDEC_SEL 53 +#define CLK_TOP_MFG_SEL 54 +#define CLK_TOP_CAMTG_SEL 55 +#define CLK_TOP_UART_SEL 56 +#define CLK_TOP_SPI_SEL 57 +#define CLK_TOP_MSDC30_0_SEL 58 +#define CLK_TOP_MSDC30_1_SEL 59 +#define CLK_TOP_MSDC30_2_SEL 60 +#define CLK_TOP_MSDC50_3_HSEL 61 +#define CLK_TOP_MSDC50_3_SEL 62 +#define CLK_TOP_AUDIO_SEL 63 +#define CLK_TOP_AUD_INTBUS_SEL 64 +#define CLK_TOP_PMICSPI_SEL 65 +#define CLK_TOP_SCP_SEL 66 +#define CLK_TOP_ATB_SEL 67 +#define CLK_TOP_MJC_SEL 68 +#define CLK_TOP_DPI0_SEL 69 +#define CLK_TOP_SCAM_SEL 70 +#define CLK_TOP_AUD_1_SEL 71 +#define CLK_TOP_AUD_2_SEL 72 +#define CLK_TOP_DPI1_SEL 73 +#define CLK_TOP_UFOENC_SEL 74 +#define CLK_TOP_UFODEC_SEL 75 +#define CLK_TOP_ETH_SEL 76 +#define CLK_TOP_ONFI_SEL 77 +#define CLK_TOP_SNFI_SEL 78 +#define CLK_TOP_HDMI_SEL 79 +#define CLK_TOP_RTC_SEL 80 +#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 81 +#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 82 + +#endif /* _DT_BINDINGS_CLOCK_MT8163_TOPCKGEN_H */ diff --git a/include/dt-bindings/reset/mediatek,mt8163-infracfg.h b/include/dt-bindings/reset/mediatek,mt8163-infracfg.h new file mode 100644 index 00000000000000..f8e686673a5333 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt8163-infracfg.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MEDIATEK_MT8163_INFRACFG_H +#define _DT_BINDINGS_RESET_MEDIATEK_MT8163_INFRACFG_H + +#define MT8163_INFRA_RST0_THERM_CTRL 0 +#define MT8163_INFRA_RST0_USB_TOP 1 +#define MT8163_INFRA_RST0_PERI_IOMMU 2 +#define MT8163_INFRA_RST0_MM_IOMMU 3 +#define MT8163_INFRA_RST0_MSDC3 4 +#define MT8163_INFRA_RST0_MSDC2 5 +#define MT8163_INFRA_RST0_MSDC1 6 +#define MT8163_INFRA_RST0_MSDC0 7 +#define MT8163_INFRA_RST0_DRAMC 8 +#define MT8163_INFRA_RST0_AP_DMA 9 +#define MT8163_INFRA_RST0_MIPI_D 10 +#define MT8163_INFRA_RST0_MIPI_C 11 +#define MT8163_INFRA_RST0_BTIF 12 +#define MT8163_INFRA_RST1_PMIC_WRAP 13 +#define MT8163_INFRA_RST1_SPM 14 +#define MT8163_INFRA_RST1_USBSIF 15 +#define MT8163_INFRA_RST1_SCP 16 +#define MT8163_INFRA_RST1_CEC 17 +#define MT8163_INFRA_RST1_IRRX 18 + +#endif /* _DT_BINDINGS_RESET_MEDIATEK_MT8163_INFRACFG_H */ From b7af53fd8716f654050c951469139e5d72c4649e Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 29 Aug 2025 22:14:46 +0100 Subject: [PATCH 005/126] clk: mediatek: Add MUX_UPD and MUX_GATE_UPD A few MediaTek SoCs (namely MT8163) do not have individual set/clr registers on muxes. Add support for those types of muxes. Signed-off-by: Ben Grisdale --- drivers/clk/mediatek/clk-mux.c | 95 ++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mux.h | 41 +++++++++++++++ 2 files changed, 136 insertions(+) diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 5f4b07e7c757b4..00f13a65a02826 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -35,6 +35,46 @@ static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw) return container_of(hw, struct mtk_clk_mux, hw); } +static int mtk_clk_mux_enable_upd(struct clk_hw *hw) +{ + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); + unsigned long flags = 0; + + if (mux->lock) + spin_lock_irqsave(mux->lock, flags); + else + __acquire(mux->lock); + + regmap_clear_bits(mux->regmap, mux->data->mux_ofs, + BIT(mux->data->gate_shift)); + + /* + * If the parent has been changed when the clock was disabled, it will + * not be effective yet. Set the update bit to ensure the mux gets + * updated. + */ + if (mux->reparent && mux->data->upd_shift >= 0) { + regmap_write(mux->regmap, mux->data->upd_ofs, + BIT(mux->data->upd_shift)); + mux->reparent = false; + } + + if (mux->lock) + spin_unlock_irqrestore(mux->lock, flags); + else + __release(mux->lock); + + return 0; +} + +static void mtk_clk_mux_disable_upd(struct clk_hw *hw) +{ + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); + + regmap_set_bits(mux->regmap, mux->data->mux_ofs, + BIT(mux->data->gate_shift)); +} + static int mtk_clk_mux_fenc_enable_setclr(struct clk_hw *hw) { struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); @@ -220,6 +260,44 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index) return 0; } +static int mtk_clk_mux_set_parent_upd_lock(struct clk_hw *hw, u8 index) +{ + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); + u32 mask = GENMASK(mux->data->mux_width - 1, 0); + u32 val, orig; + unsigned long flags = 0; + + if (mux->lock) + spin_lock_irqsave(mux->lock, flags); + else + __acquire(mux->lock); + + if (mux->data->parent_index) + index = mux->data->parent_index[index]; + + regmap_read(mux->regmap, mux->data->mux_ofs, &orig); + val = (orig & ~(mask << mux->data->mux_shift)) + | (index << mux->data->mux_shift); + + if (val != orig) { + regmap_write(mux->regmap, mux->data->mux_ofs, + val); + + if (mux->data->upd_shift >= 0) { + regmap_write(mux->regmap, mux->data->upd_ofs, + BIT(mux->data->upd_shift)); + mux->reparent = true; + } + } + + if (mux->lock) + spin_unlock_irqrestore(mux->lock, flags); + else + __release(mux->lock); + + return 0; +} + static int mtk_clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { @@ -271,6 +349,23 @@ const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops = { }; EXPORT_SYMBOL_GPL(mtk_mux_gate_hwv_fenc_clr_set_upd_ops); +const struct clk_ops mtk_mux_upd_ops = { + .get_parent = mtk_clk_mux_get_parent, + .set_parent = mtk_clk_mux_set_parent_upd_lock, + .determine_rate = mtk_clk_mux_determine_rate, +}; +EXPORT_SYMBOL_GPL(mtk_mux_upd_ops); + +const struct clk_ops mtk_mux_gate_upd_ops = { + .enable = mtk_clk_mux_enable_upd, + .disable = mtk_clk_mux_disable_upd, + .is_enabled = mtk_clk_mux_is_enabled, + .get_parent = mtk_clk_mux_get_parent, + .set_parent = mtk_clk_mux_set_parent_upd_lock, + .determine_rate = mtk_clk_mux_determine_rate, +}; +EXPORT_SYMBOL_GPL(mtk_mux_gate_upd_ops); + static struct clk_hw *mtk_clk_register_mux(struct device *dev, const struct mtk_mux *mux, struct regmap *regmap, diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index 151e56dcf88427..d05a976e6084f4 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -81,6 +81,23 @@ struct mtk_mux { _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ _gate, _upd_ofs, _upd, _flags, _ops) \ +#define GATE_UPD_FLAGS(_id, _name, _parents, _mux_ofs, _shift, _width, \ + _gate, _upd_ofs, _upd, _flags, _ops) \ + __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ + NULL, ARRAY_SIZE(_parents), _mux_ofs, \ + 0, 0, _shift, _width, _gate, _upd_ofs, \ + _upd, _flags, _ops) + +#define GATE_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \ + _mux_ofs, _shift, _width, _gate, _upd_ofs, \ + _upd, _flags, _ops) \ + __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ + _paridx, ARRAY_SIZE(_paridx), _mux_ofs, \ + 0, 0, _shift, _width, _gate, _upd_ofs, \ + _upd, _flags, _ops) + +extern const struct clk_ops mtk_mux_upd_ops; +extern const struct clk_ops mtk_mux_gate_upd_ops; extern const struct clk_ops mtk_mux_clr_set_upd_ops; extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; extern const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops; @@ -205,6 +222,30 @@ extern const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops; _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, _upd, \ _fenc_sta_mon_ofs, _fenc, 0) +#define MUX_GATE_UPD_FLAGS(_id, _name, _parents, _mux_ofs, _shift, \ + _width, _gate, _upd_ofs, _upd, _flags) \ + GATE_UPD_FLAGS(_id, _name, _parents, _mux_ofs, _shift, \ + _width, _gate, _upd_ofs, _upd, \ + _flags, mtk_mux_gate_upd_ops) + +#define MUX_GATE_UPD(_id, _name, _parents, _mux_ofs, _shift, _width, \ + _gate, _upd_ofs, _upd) \ + MUX_GATE_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, \ + CLK_SET_RATE_PARENT) + +#define MUX_UPD_FLAGS(_id, _name, _parents, _mux_ofs, _shift, _width, \ + _upd_ofs, _upd, _flags) \ + GATE_UPD_FLAGS(_id, _name, _parents, _mux_ofs, _shift, \ + _width, 0, _upd_ofs, _upd, \ + _flags, mtk_mux_upd_ops) + +#define MUX_UPD(_id, _name, _parents, _mux_ofs, _shift, _width, \ + _upd_ofs, _upd) \ + MUX_UPD_FLAGS(_id, _name, _parents, _mux_ofs, _shift, \ + _width, _upd_ofs, _upd, \ + CLK_SET_RATE_PARENT) + int mtk_clk_register_muxes(struct device *dev, const struct mtk_mux *muxes, int num, struct device_node *node, From 300024198e1bc57795cfb1c5de266a5a67129a8f Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 28 Dec 2025 22:52:11 +0000 Subject: [PATCH 006/126] clk: mediatek: Add MUX_DIV_GATE_FLAGS macro Mainly useful in circumstances where we don't want the divider to propagate rate changes to its parent. Signed-off-by: Ben Grisdale --- drivers/clk/mediatek/clk-mtk.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 5417b9264e6df9..5e455feb318a00 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -175,10 +175,10 @@ struct mtk_composite { .flags = 0, \ } -#define MUX_DIV_GATE(_id, _name, _parents, \ +#define MUX_DIV_GATE_FLAGS(_id, _name, _parents, \ _mux_reg, _mux_shift, _mux_width, \ _div_reg, _div_shift, _div_width, \ - _gate_reg, _gate_shift) { \ + _gate_reg, _gate_shift, _flags) { \ .id = _id, \ .name = _name, \ .parent_names = _parents, \ @@ -191,9 +191,19 @@ struct mtk_composite { .divider_width = _div_width, \ .gate_reg = _gate_reg, \ .gate_shift = _gate_shift, \ - .flags = CLK_SET_RATE_PARENT, \ + .flags = _flags, \ } +#define MUX_DIV_GATE(_id, _name, _parents, \ + _mux_reg, _mux_shift, _mux_width, \ + _div_reg, _div_shift, _div_width, \ + _gate_reg, _gate_shift) \ + MUX_DIV_GATE_FLAGS(_id, _name, _parents, \ + _mux_reg, _mux_shift, _mux_width, \ + _div_reg, _div_shift, _div_width, \ + _gate_reg, _gate_shift, \ + CLK_SET_RATE_PARENT) + int mtk_clk_register_composites(struct device *dev, const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, From 05b6247632bbec5a2b257266cf501a8608c8e0a5 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 16:10:36 +0100 Subject: [PATCH 007/126] clk: mediatek: Add support for MT8163 main clock controllers Add drivers to support the main clock controllers on the MT8163 SoC, including apmixedsys, infracfg and topckgen. Signed-off-by: Ben Grisdale --- drivers/clk/mediatek/Kconfig | 8 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8163-apmixedsys.c | 208 +++++++++ drivers/clk/mediatek/clk-mt8163-infracfg.c | 292 ++++++++++++ drivers/clk/mediatek/clk-mt8163-topckgen.c | 468 +++++++++++++++++++ 5 files changed, 977 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8163-apmixedsys.c create mode 100644 drivers/clk/mediatek/clk-mt8163-infracfg.c create mode 100644 drivers/clk/mediatek/clk-mt8163-topckgen.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 2c09fd729bab04..bf2ef045ae246c 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -477,6 +477,14 @@ config COMMON_CLK_MT8135 help This driver supports MediaTek MT8135 clocks. +config COMMON_CLK_MT8163 + tristate "Clock driver for MediaTek MT8163" + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK + help + This driver supports MediaTek MT8163 basic clocks. + config COMMON_CLK_MT8167 tristate "Clock driver for MediaTek MT8167" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index d8736a060dbdca..b7c2896d3a8ee7 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135-apmixedsys.o clk-mt8135.o +obj-$(CONFIG_COMMON_CLK_MT8163) += clk-mt8163-apmixedsys.o clk-mt8163-infracfg.o clk-mt8163-topckgen.o obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167-apmixedsys.o clk-mt8167.o obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o obj-$(CONFIG_COMMON_CLK_MT8167_IMGSYS) += clk-mt8167-img.o diff --git a/drivers/clk/mediatek/clk-mt8163-apmixedsys.c b/drivers/clk/mediatek/clk-mt8163-apmixedsys.c new file mode 100644 index 00000000000000..23e63c924bf079 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8163-apmixedsys.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 MediaTek Inc. + * James Liao + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" + +#include + +#define REG_REF2USB 0x8 + +#define MT8163_PLL_FMAX (2500UL * MHZ) + +#define CON0_MT8163_RST_BAR BIT(24) + +static const struct mtk_gate_regs apmixed_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ + _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) + +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) + +/* + * CRITICAL CLOCK: + * apmixed_armpll26m is the toppest clock gate of all PLLs. + */ +static const struct mtk_gate apmixed_clks[] = { + GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", "clk26m", 4), + GATE_APMIXED_FLAGS(CLK_APMIXED_ARMPLL_26M, "apmixed_armpll26m", + "clk26m", 5, CLK_IS_CRITICAL), + GATE_APMIXED(CLK_APMIXED_MIPI_26M, "apmixed_mipi26m", "clk26m", 6), +}; + +#define _PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _div_table) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = CON0_MT8163_RST_BAR, \ + .fmax = MT8163_PLL_FMAX, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .tuner_en_reg = _tuner_en_reg, \ + .tuner_en_bit = _tuner_en_bit, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_table = _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift) \ + _PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, 0, 0, _pcw_reg, _pcw_shift, \ + NULL) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift, _div_table) \ + _PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, 0, 0, _pcw_reg, _pcw_shift, \ + _div_table) + +#define PLL_C(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, \ + _pcw_shift) \ + _PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + NULL) + +static const struct mtk_pll_div_table armpll_div_table[] = { + { .div = 0, .freq = MT8163_PLL_FMAX }, + { .div = 1, .freq = 1001000000 }, + { .div = 2, .freq = 520000000 }, + { .div = 3, .freq = 260000000 }, + { .div = 4, .freq = 130000000 }, + { /* sentinel */} +}; + +static const struct mtk_pll_div_table mmpll_div_table[] = { + { .div = 0, .freq = MT8163_PLL_FMAX }, + { .div = 1, .freq = 1000000000 }, + { .div = 2, .freq = 625000000 }, + { .div = 3, .freq = 253500000 }, + { .div = 4, .freq = 126750000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_data plls[] = { + PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x210, 0x21c, 0x1, PLL_AO, 21, 0x214, 24, 0x0, 0x214, 0, armpll_div_table), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0x1, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0x1, HAVE_RST_BAR, 21, 0x230, 4, 0x0, 0x234, 0), + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x1, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x1, 0, 21, 0x250, 4, 0x0, 0x254, 0), + PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x1, 0, 21, 0x260, 4, 0x0, 0x264, 0), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x1, 0, 21, 0x270, 4, 0x0, 0x274, 0), + PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x1, 0, 21, 0x280, 4, 0x0, 0x284, 0), + PLL_C(CLK_APMIXED_AUD1PLL, "aud1pll", 0x2a0, 0x2ac, 0x1, 0, 31, 0x2a0, 4, 0x300, 0x014, 10, 0x2a4, 0), + PLL_C(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2b0, 0x2bc, 0x1, 0, 31, 0x2b0, 4, 0x304, 0x014, 11, 0x2b4, 0), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2c0, 0x2cc, 0x1, 0, 21, 0x2c0, 4, 0x0, 0x2c4, 0), +}; + +static const struct of_device_id of_match_clk_mt8163_apmixed[] = { + { .compatible = "mediatek,mt8163-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8163_apmixed); + +static int clk_mt8163_apmixed_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + void __iomem *base; + struct clk_hw *hw; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + goto free_clk_data; + + ret = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + if (ret) + goto unregister_plls; + + hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REG_REF2USB); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + dev_err(dev, "Failed to register ref2usb_tx: %d\n", ret); + goto unregister_gates; + } + clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) { + dev_err(dev, "Cannot register clock provider: %d\n", ret); + goto unregister_ref2usb; + } + + return 0; + +unregister_ref2usb: + mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); +unregister_gates: + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return ret; +} + +static void clk_mt8163_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); +} + +static struct platform_driver clk_mt8163_apmixed_drv = { + .probe = clk_mt8163_apmixed_probe, + .remove = clk_mt8163_apmixed_remove, + .driver = { + .name = "clk-mt8163-apmixed", + .of_match_table = of_match_clk_mt8163_apmixed, + }, +}; +module_platform_driver(clk_mt8163_apmixed_drv); + +MODULE_AUTHOR("James Liao "); +MODULE_AUTHOR("Ben Grisdale "); +MODULE_DESCRIPTION("MediaTek MT8163 apmixed clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8163-infracfg.c b/drivers/clk/mediatek/clk-mt8163-infracfg.c new file mode 100644 index 00000000000000..575697bc5df002 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8163-infracfg.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 MediaTek Inc. + * James Liao + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include + +#include "clk-cpumux.h" +#include "clk-gate.h" +#include "clk-mtk.h" + +#include +#include + +#define RST_NR_PER_BANK 32 + +static DEFINE_SPINLOCK(mt8163_peri_clk_lock); + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x0080, + .clr_ofs = 0x0084, + .sta_ofs = 0x0090, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x0088, + .clr_ofs = 0x008c, + .sta_ofs = 0x0094, +}; + +#define GATE_ICG0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_ICG0_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + +#define GATE_ICG1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + +static const struct mtk_gate infracfg_gates[] = { + /* INFRA0 */ + GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "clk26m", 0), + GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "clk26m", 1), + GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "clk26m", 2), + GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "clk26m", 3), + GATE_ICG0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4), + GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5), + GATE_ICG0_FLAGS(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", + 6, CLK_IS_CRITICAL), + GATE_ICG0(CLK_INFRA_USB, "infra_usb", "axi_sel", 7), + GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "axi_sel", 8), + GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9), + GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), + GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11), + GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12), + GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13), + GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15), + GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16), + GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17), + GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18), + GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21), + GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), + GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), + GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), + GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), + GATE_ICG0(CLK_INFRA_USB_MCU, "infra_usb_mcu", "axi_sel", 26), + GATE_ICG0(CLK_INFRA_NFI_ECC_66M, "infra_nfi_ecc66", "axi_sel", 27), + GATE_ICG0(CLK_INFRA_NFI_66M, "infra_nfi_66m", "axi_sel", 28), + GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), + + /* INFRA1 */ + GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1), + GATE_ICG1(CLK_INFRA_MSDC3, "infra_msdc3", "msdc50_3_sel", 2), + GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4), + GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5), + GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc30_0_sel", 6), + GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), + GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), + GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10), + GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), + GATE_ICG1(CLK_INFRA_IRRX, "infra_irrx", "rtc_sel", 12), + GATE_ICG1(CLK_INFRA_UFO, "infra_ufo", "axi_sel", 13), + GATE_ICG1(CLK_INFRA_CEC, "infra_cec", "rtc_sel", 14), + GATE_ICG1(CLK_INFRA_CEC_26M, "infra_cec_26m", "clk26m", 15), + GATE_ICG1(CLK_INFRA_NFI_BCLK, "infra_nfi_bclk", "spi_sel", 16), + GATE_ICG1(CLK_INFRA_NFI_ECC, "infra_nfi_ecc", "spi_sel", 17), + GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18), + GATE_ICG1(CLK_INFRA_XIU, "infra_xiu", "axi_sel", 19), + GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_devapc", "axi_sel", 20), + GATE_ICG1(CLK_INFRA_XIU2AHB, "infra_xiu2ahb", "axi_sel", 21), + GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 22), + GATE_ICG1(CLK_INFRA_ETH_50M, "infra_eth_50m", "eth_sel", 23), + GATE_ICG1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), + GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), + GATE_ICG1(CLK_INFRA_ETH_25M, "infra_eth_25m", "eth_sel", 26), + GATE_ICG1(CLK_INFRA_NFI, "infra_nfi", "axi_sel", 27), + GATE_ICG1(CLK_INFRA_ONFI, "infra_onfi", "onfi_sel", 28), + GATE_ICG1(CLK_INFRA_SNFI, "infra_snfi", "snfi_sel", 29), + GATE_ICG1(CLK_INFRA_ETH, "infra_eth", "axi_sel", 30), + GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_26m", "clk26m", + 31, CLK_IS_CRITICAL), +}; + +static const struct mtk_fixed_factor infra_divs[] = { + FACTOR(CLK_INFRA_OSC, "osc_ck", "clk26m", 8, 1), + FACTOR(CLK_INFRA_OSC_D8, "osc_d8", "osc_ck", 1, 8), + FACTOR(CLK_INFRA_OSC_D16, "osc_d16", "osc_ck", 1, 16), + FACTOR(CLK_INFRA_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8), + FACTOR(CLK_INFRA_ETH_D2, "eth_d2", "eth_sel", 1, 2), + FACTOR(CLK_INFRA_ONFI_D2, "onfi_d2", "onfi_sel", 1, 2), +}; + +static const char * const infra_uart_parents[] = { + "clk26m", + "uart_sel" +}; + +static const char * const infra_spi_parents[] = { + "axi_sel", + "spi_sel" +}; + +static const char * const infra_dramc_parents[] = { + "clk26m", + "clk26m_d8" +}; + +static const char * const infra_ulp_parents[] = { + "osc_d8", + "osc_d16" +}; + +static const char * const infra_eth_parents[] = { + "eth_d2", + "eth_sel" +}; + +static const char * const infra_nfi_parents[] = { + "axi_sel", + "onfi_d2" +}; + +static const char * const infra_ca53_parents[] = { + "clk26m", + "armpll", + "arm_div_pll1_en", + "arm_div_pll2_en", +}; + +static const struct mtk_composite infracfg_muxes[] = { + MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart_parents, 0x098, 0, 1), + MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart_parents, 0x098, 1, 1), + MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart_parents, 0x098, 2, 1), + MUX(CLK_INFRA_UART3_SEL, "infra_uart3_sel", infra_uart_parents, 0x098, 3, 1), + MUX(CLK_INFRA_SPI_SEL, "infra_spi_sel", infra_spi_parents, 0x098, 4, 1), + MUX(CLK_INFRA_DRAMC_SEL, "infra_dramc_sel", infra_dramc_parents, 0x098, 7, 1), + MUX(CLK_INFRA_ULPOSC_SEL, "infra_ulp_sel", infra_ulp_parents, 0x098, 8, 1), + MUX(CLK_INFRA_ETH_25M_SEL, "infra_eth_sel", infra_eth_parents, 0x098, 9, 1), + MUX(CLK_INFRA_NFI_SEL, "infra_nfi_sel", infra_nfi_parents, 0x098, 10, 1), +}; + +static const struct mtk_composite cpu_muxes[] = { + MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", infra_ca53_parents, 0x0000, 0, 2), +}; + +static u16 infracfg_rst_bank_ofs[] = { 0x120, 0x140 }; + +static u16 infracfg_rst_idx_map[] = { + /* INFRA_GLOBALCON_RST_0 */ + [MT8163_INFRA_RST0_THERM_CTRL] = 0 * RST_NR_PER_BANK + 0, + [MT8163_INFRA_RST0_USB_TOP] = 0 * RST_NR_PER_BANK + 1, + [MT8163_INFRA_RST0_PERI_IOMMU] = 0 * RST_NR_PER_BANK + 2, + [MT8163_INFRA_RST0_MM_IOMMU] = 0 * RST_NR_PER_BANK + 3, + [MT8163_INFRA_RST0_MSDC3] = 0 * RST_NR_PER_BANK + 4, + [MT8163_INFRA_RST0_MSDC2] = 0 * RST_NR_PER_BANK + 5, + [MT8163_INFRA_RST0_MSDC1] = 0 * RST_NR_PER_BANK + 6, + [MT8163_INFRA_RST0_MSDC0] = 0 * RST_NR_PER_BANK + 7, + [MT8163_INFRA_RST0_DRAMC] = 0 * RST_NR_PER_BANK + 8, + [MT8163_INFRA_RST0_AP_DMA] = 0 * RST_NR_PER_BANK + 9, + [MT8163_INFRA_RST0_MIPI_D] = 0 * RST_NR_PER_BANK + 10, + [MT8163_INFRA_RST0_MIPI_C] = 0 * RST_NR_PER_BANK + 11, + [MT8163_INFRA_RST0_BTIF] = 0 * RST_NR_PER_BANK + 12, + + /* INFRA_GLOBALCON_RST_1 */ + [MT8163_INFRA_RST1_PMIC_WRAP] = 1 * RST_NR_PER_BANK + 0, + [MT8163_INFRA_RST1_SPM] = 1 * RST_NR_PER_BANK + 1, + [MT8163_INFRA_RST1_USBSIF] = 1 * RST_NR_PER_BANK + 2, + [MT8163_INFRA_RST1_SCP] = 1 * RST_NR_PER_BANK + 3, + [MT8163_INFRA_RST1_CEC] = 1 * RST_NR_PER_BANK + 4, + [MT8163_INFRA_RST1_IRRX] = 1 * RST_NR_PER_BANK + 5, +}; + +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = infracfg_rst_bank_ofs, + .rst_bank_nr = ARRAY_SIZE(infracfg_rst_bank_ofs), + .rst_idx_map = infracfg_rst_idx_map, + .rst_idx_map_nr = ARRAY_SIZE(infracfg_rst_idx_map) +}; + +static int clk_mt8163_infracfg_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + void __iomem *base; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); + if (ret) + goto free_clk_data; + + ret = mtk_clk_register_gates(&pdev->dev, node, infracfg_gates, + ARRAY_SIZE(infracfg_gates), clk_data); + if (ret) + goto free_clk_data; + + ret = mtk_clk_register_composites(&pdev->dev, infracfg_muxes, + ARRAY_SIZE(infracfg_muxes), base, + &mt8163_peri_clk_lock, clk_data); + if (ret) + goto unregister_gates; + + ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, + ARRAY_SIZE(cpu_muxes), clk_data); + if (ret) + goto unregister_composites; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_cpumuxes; + + return 0; + +unregister_cpumuxes: + mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); +unregister_composites: + mtk_clk_unregister_composites(infracfg_muxes, ARRAY_SIZE(infracfg_muxes), clk_data); +unregister_gates: + mtk_clk_unregister_gates(infracfg_gates, ARRAY_SIZE(infracfg_gates), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return ret; +} + +static void clk_mt8163_infracfg_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); + mtk_clk_unregister_composites(infracfg_muxes, ARRAY_SIZE(infracfg_muxes), clk_data); + mtk_clk_unregister_gates(infracfg_gates, ARRAY_SIZE(infracfg_gates), clk_data); + mtk_free_clk_data(clk_data); +} + +static const struct of_device_id of_match_clk_mt8163_infracfg[] = { + { .compatible = "mediatek,mt8163-infracfg" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8163_infracfg); + +static struct platform_driver clk_mt8163_infracfg_drv = { + .driver = { + .name = "clk-mt8163-infracfg", + .of_match_table = of_match_clk_mt8163_infracfg, + }, + .probe = clk_mt8163_infracfg_probe, + .remove = clk_mt8163_infracfg_remove, +}; +module_platform_driver(clk_mt8163_infracfg_drv); + +MODULE_AUTHOR("James Liao "); +MODULE_AUTHOR("Ben Grisdale "); +MODULE_DESCRIPTION("MediaTek MT8163 infracfg clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8163-topckgen.c b/drivers/clk/mediatek/clk-mt8163-topckgen.c new file mode 100644 index 00000000000000..8b48b9266f7834 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8163-topckgen.c @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 MediaTek Inc. + * James Liao + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include + +static DEFINE_SPINLOCK(mt8163_topckgen_lock); + +static const struct mtk_fixed_clk topckgen_fixed_clks[] = { + FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 0), + FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 75 * MHZ), + FIXED_CLK(CLK_TOP_F26M_MEM_CKGEN_OCC, "f26m_mem_ckgen", "clk26m", 26 * MHZ), + FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 52500000), +}; + +static const struct mtk_fixed_factor topckgen_factors[] = { + FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2), + FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3), + FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5), + FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7), + + FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2), + FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3), + FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5), + FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7), + FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26), + + FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793), + + FACTOR(CLK_TOP_HDMI_CTS, "hdmi_cts_ck", "hdmitx_dig_cts", 1, 2), + FACTOR(CLK_TOP_HDMI_CTS_D2, "hdmi_cts_d2", "hdmitx_dig_cts", 1, 3), + FACTOR(CLK_TOP_HDMI_CTS_D3, "hdmi_cts_d3", "hdmitx_dig_cts", 1, 2), + + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), + FACTOR(CLK_TOP_LVDSPLL_ETH, "lvdspll_eth_ck", "lvdspll", 1, 4), + + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), + + FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "main_h218p4m", 2, 1), + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2), + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4), + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8), + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16), + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2), + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4), + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "main_h364m", 1, 8), + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2), + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4), + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2), + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4), + + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), + FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), + FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), + + FACTOR(CLK_TOP_UNIVPLL_D2P5, "univpll_d2p5", "univ_249p6m", 2, 1), + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2), + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4), + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2), + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4), + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8), + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2), + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4), + FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8), +}; + +static const char * const axi_parents[] = { + "clk26m", + "syspll1_d4" +}; + +static const char * const mem_parents[] = { + "clk26m", + "dmpll_ck", + "f26m_mem_ckgen" +}; + +static const char * const ddrphycfg_parents[] = { + "clk26m", + "syspll1_d8" +}; + +static const char * const mm_parents[] = { + "clk26m", + "main_h364m", + "univ_416m", + "vencpll" +}; + +static const char * const pwm_parents[] = { + "clk26m", + "univpll2_d2", + "univpll2_d4" +}; + +static const char * const vdec_parents[] = { + "clk26m", + "main_h364m", + "syspll1_d2", + "univpll1_d2", + "syspll1_d4" +}; + +static const char * const mfg_parents[] = { + "clk26m", + "mmpll", + "univ_416m", + "main_h364m" +}; + +static const char * const camtg_parents[] = { + "clk26m", + "univ_48m", + "univpll2_d2" +}; + +static const char * const uart_parents[] = { + "clk26m", + "univpll2_d8" +}; + +static const char * const spi_parents[] = { + "clk26m", + "syspll3_d2" +}; + +static const char * const msdc30_0_parents[] = { + "clk26m", + "univpll2_d2", + "msdcpll_d2", + "univpll1_d4", + "syspll2_d2", + "main_h156m", + "univ_178p3m" +}; + +static const char * const msdc30_1_parents[] = { + "clk26m", + "univpll2_d2", + "msdcpll_d2", + "univpll1_d4", + "syspll2_d2", + "main_h156m", + "univ_178p3m" +}; + +static const char * const msdc30_2_parents[] = { + "clk26m", + "univpll2_d2", + "msdcpll_d2", + "univpll1_d4", + "syspll2_d2", + "main_h156m", + "univ_178p3m" +}; + +static const char * const msdc50_3_h_parents[] = { + "clk26m", + "syspll1_d2", + "syspll2_d2", + "syspll4_d2" +}; + +static const char * const msdc50_3_parents[] = { + "clk26m", + "msdcpll", + "msdcpll_d2", + "univpll1_d4", + "syspll2_d2", + "main_h156m", + "msdcpll_d4", + "univ_624m", + "univpll1_d2" +}; + +static const char * const audio_parents[] = { + "clk26m", + "syspll3_d4", + "syspll4_d4", + "syspll1_d16" +}; + +static const char * const aud_intbus_parents[] = { + "clk26m", + "syspll1_d4", + "syspll4_d2" +}; + +static const char * const pmicspi_parents[] = { + "clk26m", + "univ_48m" +}; + +static const char * const scp_parents[] = { + "clk26m", + "mpll", + "syspll1_d4" +}; + +static const char * const atb_parents[] = { + "clk26m", + "syspll1_d2" +}; + +static const char * const mjc_parents[] = { + "clk26m", + "main_h218p4m", + "univ_249p6m" +}; + +static const char * const dpi0_parents[] = { + "clk26m", + "lvdspll", + "lvdspll_d2", + "lvdspll_d4", + "lvdspll_d8" +}; + +static const char * const scam_parents[] = { + "clk26m", + "syspll3_d2" +}; + +static const char * const aud_1_parents[] = { + "clk26m", + "aud1pll" +}; + +static const char * const aud_2_parents[] = { + "clk26m", + "aud2pll" +}; + +static const char * const dpi1_parents[] = { + "clk26m", + "tvdpll_d2", + "tvdpll_d4", + "tvdpll_d8", + "tvdpll_d16" +}; + +static const char * const ufoenc_parents[] = { + "clk26m", + "univ_624m", + "main_h546m", + "univpll_d2p5", + "syspll_d2p5", + "univ_416m", + "main_h364m", + "syspll1_d2" +}; + +static const char * const ufodec_parents[] = { + "clk26m", + "main_h546m", + "univpll_d2p5", + "syspll_d2p5", + "univ_416m", + "main_h364m", + "syspll1_d2" +}; + +static const char * const eth_parents[] = { + "clk26m", + "syspll3_d4", + "univpll2_d8", + "lvdspll_eth_ck", + "univ_48m", + "syspll2_d8", + "syspll4_d4", + "univpll3_d8", + "clk26m" +}; + +static const char * const onfi_parents[] = { + "clk26m", + "syspll2_d2", + "main_h156m", + "univpll3_d2", + "syspll2_d4", + "univpll3_d4", + "syspll4_d4" +}; + +static const char * const snfi_parents[] = { + "clk26m", + "univpll2_d8", + "univpll3_d4", + "syspll4_d2", + "univpll2_d4", + "univpll3_d2", + "syspll1_d4", + "univpll1_d4", + "clk26m" +}; + +static const char * const hdmi_parents[] = { + "clk26m", + "hdmi_cts_ck", + "hdmi_cts_d2", + "hdmi_cts_d3" +}; + +static const char * const rtc_parents[] = { + "clkrtc_int", + "clk32k", + "clk26m", + "univpll3_d8" +}; + +static const struct mtk_mux topckgen_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, + 0x0040, 0, 1, 7, 0x0004, 0, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, + 0x0040, 8, 2, 15, 0x0004, 1, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_UPD_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, + 0x0040, 16, 1, 23, 0x0004, 2, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, + 0x0040, 24, 2, 31, 0x0004, 3), + + /* CLK_CFG_1 */ + MUX_GATE_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, + 0x0050, 0, 2, 7, 0x0004, 4), + MUX_GATE_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, + 0x0050, 8, 3, 15, 0x0004, 5), + MUX_GATE_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, + 0x0050, 24, 2, 31, 0x0004, 7), + + /* CLK_CFG_2 */ + MUX_GATE_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, + 0x0060, 0, 2, 7, 0x0004, 8), + MUX_GATE_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, + 0x0060, 8, 1, 15, 0x0004, 9), + MUX_GATE_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, + 0x0060, 16, 1, 23, 0x0004, 10), + + /* CLK_CFG_3 */ + MUX_GATE_UPD(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents, + 0x0070, 0, 3, 7, 0x0004, 12), + MUX_GATE_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, + 0x0070, 8, 3, 15, 0x0004, 13), + MUX_GATE_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, + 0x0070, 16, 3, 23, 0x0004, 14), + + /* CLK_CFG_4 */ + MUX_GATE_UPD(CLK_TOP_MSDC50_3_HSEL, "msdc50_3_hsel", msdc50_3_h_parents, + 0x0080, 0, 2, 7, 0x0004, 15), + MUX_GATE_UPD(CLK_TOP_MSDC50_3_SEL, "msdc50_3_sel", msdc50_3_parents, + 0x0080, 8, 4, 15, 0x0004, 16), + MUX_GATE_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, + 0x0080, 16, 2, 23, 0x0004, 17), + MUX_GATE_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, + 0x0080, 24, 2, 31, 0x0004, 18), + + /* CLK_CFG_5 */ + MUX_GATE_UPD(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, + 0x0090, 0, 1, 7, 0x0004, 19), + MUX_GATE_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, + 0x0090, 8, 2, 15, 0x0004, 20), + MUX_GATE_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, + 0x0090, 16, 1, 23, 0x0004, 21), + MUX_GATE_UPD(CLK_TOP_MJC_SEL, "mjc_sel", mjc_parents, + 0x0090, 24, 2, 31, 0x0004, 22), + + /* CLK_CFG_6 */ + /* + * The dpi0_sel clock should not propagate rate changes to its parent + * clock so the dpi driver can have full control over PLL and divider. + */ + MUX_GATE_UPD_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, + 0x00a0, 0, 3, 7, 0x0004, 23, + 0), + MUX_GATE_UPD(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, + 0x00a0, 8, 1, 15, 0x0004, 24), + MUX_GATE_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, + 0x00a0, 16, 1, 23, 0x0004, 25), + MUX_GATE_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, + 0x00a0, 24, 1, 31, 0x0004, 26), + + /* CLK_CFG_7 */ + MUX_GATE_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, + 0x00b0, 0, 3, 7, 0x0004, 6), + MUX_GATE_UPD(CLK_TOP_UFOENC_SEL, "ufoenc_sel", ufoenc_parents, + 0x00b0, 8, 3, 15, 0x0004, 27), + MUX_GATE_UPD(CLK_TOP_UFODEC_SEL, "ufodec_sel", ufodec_parents, + 0x00b0, 16, 3, 23, 0x0004, 28), + MUX_GATE_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, + 0x00b0, 24, 4, 31, 0x0004, 29), + + /* CLK_CFG_8 */ + MUX_GATE_UPD(CLK_TOP_ONFI_SEL, "onfi_sel", onfi_parents, + 0x00c0, 0, 3, 7, 0x0004, 30), + MUX_GATE_UPD(CLK_TOP_SNFI_SEL, "snfi_sel", snfi_parents, + 0x00c0, 8, 2, 15, 0x0004, 31), + MUX_GATE_UPD(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, + 0x00c0, 16, 2, 23, 0x0004, 11), + MUX_GATE_UPD_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, + 0x00c0, 24, 2, 31, 0x0008, 0, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), +}; + +static const struct mtk_gate_regs top_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x104, + .sta_ofs = 0x104, +}; + +#define GATE_TOP(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + +static const struct mtk_gate topckgen_gates[] = { + /* CLK_MISC_CFG_0 */ + GATE_TOP(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN, + "arm_div_pll1_en", "mainpll", 4), + GATE_TOP(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN, + "arm_div_pll2_en", "univpll", 5), +}; + +static const struct mtk_clk_desc topckgen_desc = { + .clks = topckgen_gates, + .num_clks = ARRAY_SIZE(topckgen_gates), + .fixed_clks = topckgen_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(topckgen_fixed_clks), + .factor_clks = topckgen_factors, + .num_factor_clks = ARRAY_SIZE(topckgen_factors), + .mux_clks = topckgen_muxes, + .num_mux_clks = ARRAY_SIZE(topckgen_muxes), + .clk_lock = &mt8163_topckgen_lock, +}; + +static const struct of_device_id of_match_mt8163_topckgen[] = { + { .compatible = "mediatek,mt8163-topckgen", .data = &topckgen_desc}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_mt8163_topckgen); + +static struct platform_driver clk_mt8163_topckgen = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8163-topckgen", + .of_match_table = of_match_mt8163_topckgen, + }, +}; +module_platform_driver(clk_mt8163_topckgen); + +MODULE_AUTHOR("James Liao "); +MODULE_AUTHOR("Ben Grisdale "); +MODULE_DESCRIPTION("MediaTek MT8163 topckgen clock driver"); +MODULE_LICENSE("GPL"); From 5fa93e975d026372693d40eb4c3b7793900b1743 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 17:38:59 +0100 Subject: [PATCH 008/126] dt-bindings: reset: Add bindings for MT8163 TOPRGU/WDT Add DT bindings for the Top Reset Generation Unit (TOPRGU) on the MT8163 SoC. Signed-off-by: Ben Grisdale --- .../bindings/watchdog/mediatek,mtk-wdt.yaml | 1 + .../dt-bindings/reset/mediatek,mt8163-wdt.h | 24 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt8163-wdt.h diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml index 953629cb9558b1..86b43196b534e7 100644 --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt6795-wdt - mediatek,mt7986-wdt - mediatek,mt7988-wdt + - mediatek,mt8163-wdt - mediatek,mt8183-wdt - mediatek,mt8186-wdt - mediatek,mt8188-wdt diff --git a/include/dt-bindings/reset/mediatek,mt8163-wdt.h b/include/dt-bindings/reset/mediatek,mt8163-wdt.h new file mode 100644 index 00000000000000..98d043ae83249f --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt8163-wdt.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8163 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8163 + +/* TOPRGU resets */ +#define MT8163_TOPRGU_INFRA_RST 0 +#define MT8163_TOPRGU_MM_RST 1 +#define MT8163_TOPRGU_MFG_RST 2 +#define MT8163_TOPRGU_VENC_RST 3 +#define MT8163_TOPRGU_VDEC_RST 4 +#define MT8163_TOPRGU_IMG_RST 5 +#define MT8163_TOPRGU_DDRPHY_RST 6 +#define MT8163_TOPRGU_MD_RST 7 +#define MT8163_TOPRGU_INFRA_AO_RS 8 +#define MT8163_TOPRGU_CONN_RST 9 +#define MT8163_TOPRGU_APMIXED_RST 10 +#define MT8163_TOPRGU_PWRAP_SPICTL_RST 11 +#define MT8163_TOPRGU_CONN_MCU_RST 12 +#define MT8163_TOPRGU_MJC_RST 13 +#define MT8163_TOPRGU_MDLITE_RST 14 +#define MT8163_TOPRGU_RST_NUM 15 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8163 */ From b989590bfee287902f9dd3fa6c2cc05f7f225a20 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 17:42:45 +0100 Subject: [PATCH 009/126] watchdog: mtk_wdt: Add support for MT8163 TOPRGU/WDT Add the compatible data for the Top Reset Generation Unit found on the MT8163 SoC. Signed-off-by: Ben Grisdale --- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 91d110646e16f7..15b407fa1f9594 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -105,6 +106,10 @@ static const struct mtk_wdt_data mt7988_data = { .has_swsysrst_en = true, }; +static const struct mtk_wdt_data mt8163_data = { + .toprgu_sw_rst_num = MT8163_TOPRGU_RST_NUM +}; + static const struct mtk_wdt_data mt8183_data = { .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, }; @@ -498,6 +503,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data }, + { .compatible = "mediatek,mt8163-wdt", .data = &mt8163_data }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data }, From 495ecfe822a2a44c422a2f6d406426cfdbce960e Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 17:59:13 +0100 Subject: [PATCH 010/126] arm64: dts: mediatek: mt8163: Add clock controllers Add the apmixedsys, infracfg and topckgen clock controllers to the MT8163 devicetree. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index c858a61ccd89ee..5dec972a353fe7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -5,6 +5,11 @@ #include +#include +#include +#include +#include + / { #address-cells = <2>; #size-cells = <2>; @@ -131,6 +136,19 @@ #size-cells = <2>; ranges; + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt8163-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: clock-controller@10001000 { + compatible = "mediatek,mt8163-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + timer: timer@10008000 { compatible = "mediatek,mt8163-timer", "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x1000>; @@ -139,6 +157,12 @@ clock-names = "system-clk", "rtc-clk"; }; + apmixedsys: clock-controller@1000c000 { + compatible = "mediatek,mt8163-apmixedsys"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + sysirq: intpol-controller@10200620 { compatible = "mediatek,mt8163-sysirq", "mediatek,mt6577-sysirq"; reg = <0 0x10200620 0 0x20>; From 3f03e847d6db30630cabebed69105bcf2b5b0a9d Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Tue, 9 Sep 2025 16:33:14 +0100 Subject: [PATCH 011/126] arm64: dts: mediatek: mt8163: Use real RTC clock for timer Now that support for basic clocks are implemented on MT8163, use the real clock for the timer. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 5dec972a353fe7..5fe470a69effb9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -102,12 +102,6 @@ clock-frequency = <13000000>; #clock-cells = <0>; }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; }; pmu { @@ -153,7 +147,7 @@ compatible = "mediatek,mt8163-timer", "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x1000>; interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; + clocks = <&system_clk>, <&topckgen CLK_TOP_RTC_SEL>; clock-names = "system-clk", "rtc-clk"; }; From 7c79354bc0f4b9c5e4d48679fbf3997ac9dfcd62 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 18:01:05 +0100 Subject: [PATCH 012/126] arm64: dts: mediatek: mt8163: Add TOPRGU / WDT Add device tree node for the Top Reset Generator Unit (TOPRGU) on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 5fe470a69effb9..518a982f960d53 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { #address-cells = <2>; @@ -143,6 +144,13 @@ #reset-cells = <1>; }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8163-wdt"; + reg = <0 0x10007000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + }; + timer: timer@10008000 { compatible = "mediatek,mt8163-timer", "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x1000>; From a7670cd6ccdfe6d124ec985587b2b8eeee1325f9 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 18:59:58 +0100 Subject: [PATCH 013/126] dt-bindings: soc: mediatek: Add binding for MT8163 PMIC Wrapper Add a compatible string for the PMIC Wrapper (PWRAP) on the MT8163 SoC. Signed-off-by: Ben Grisdale --- .../devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index e7c4a3984c601f..fe7a2c6f1173f5 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -38,6 +38,7 @@ properties: - mediatek,mt6873-pwrap - mediatek,mt7622-pwrap - mediatek,mt8135-pwrap + - mediatek,mt8163-pwrap - mediatek,mt8173-pwrap - mediatek,mt8183-pwrap - mediatek,mt8186-pwrap From 4779497aae689dc845663b1b63e01b66e184d1b2 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 19:03:10 +0100 Subject: [PATCH 014/126] dt-bindings: mfd: Add mediatek,mt8163-pctl-a-syscfg binding Add a binding for mediatek,mt8163-pctl-a-syscfg. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index e2286708806314..084f2595db8e14 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -90,6 +90,7 @@ select: - mediatek,mt7988-topmisc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg + - mediatek,mt8163-pctl-a-syscfg - mediatek,mt8173-pctl-a-syscfg - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon From 85fcb91cd05245bf62137928a7e09afe7c32b7a8 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 20:43:42 +0100 Subject: [PATCH 015/126] dt-bindings: pinctrl: Add bindings for MT8163 pinctrl Add bindings for pinctrl on the MT8163 SoC. Signed-off-by: Ben Grisdale --- .../pinctrl/mediatek,mt65xx-pinctrl.yaml | 1 + include/dt-bindings/pinctrl/mt8163-pinfunc.h | 822 ++++++++++++++++++ 2 files changed, 823 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt8163-pinfunc.h diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index aa71398cf522fd..6be43d082bab9b 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt7623-pinctrl - mediatek,mt8127-pinctrl - mediatek,mt8135-pinctrl + - mediatek,mt8163-pinctrl - mediatek,mt8167-pinctrl - mediatek,mt8173-pinctrl - mediatek,mt8516-pinctrl diff --git a/include/dt-bindings/pinctrl/mt8163-pinfunc.h b/include/dt-bindings/pinctrl/mt8163-pinfunc.h new file mode 100644 index 00000000000000..35424ca92017f7 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8163-pinfunc.h @@ -0,0 +1,822 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015 MediaTek Inc. + */ + +#ifndef __DTS_MT8163_PINFUNC_H +#define __DTS_MT8163_PINFUNC_H + +#include + +#define MT8163_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8163_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(0) | 1) +#define MT8163_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(0) | 2) + +#define MT8163_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8163_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(1) | 1) +#define MT8163_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(1) | 2) + +#define MT8163_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8163_PIN_2_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(2) | 1) +#define MT8163_PIN_2_PWRAP_INT__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 4) +#define MT8163_PIN_2_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 5) +#define MT8163_PIN_2_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(2) | 6) + +#define MT8163_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8163_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(3) | 1) + +#define MT8163_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8163_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(4) | 1) + +#define MT8163_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8163_PIN_5_PWRAP_SPI0_CK2__FUNC_I2S0_MCK (MTK_PIN_NO(5) | 1) +#define MT8163_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 2) +#define MT8163_PIN_5_PWRAP_SPI0_CK2__FUNC_VDEC_TEST_CK (MTK_PIN_NO(5) | 3) +#define MT8163_PIN_5_PWRAP_SPI0_CK2__FUNC_I2S1_MCK (MTK_PIN_NO(5) | 4) +#define MT8163_PIN_5_PWRAP_SPI0_CK2__FUNC_I2S2_MCK (MTK_PIN_NO(5) | 5) +#define MT8163_PIN_5_PWRAP_SPI0_CK2__FUNC_I2S3_MCK (MTK_PIN_NO(5) | 6) +#define MT8163_PIN_5_PWRAP_SPI0_CK2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(5) | 7) + +#define MT8163_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8163_PIN_6_PWRAP_SPI0_CSN2__FUNC_I2S0_MCK (MTK_PIN_NO(6) | 1) +#define MT8163_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 2) +#define MT8163_PIN_6_PWRAP_SPI0_CSN2__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 3) +#define MT8163_PIN_6_PWRAP_SPI0_CSN2__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 4) +#define MT8163_PIN_6_PWRAP_SPI0_CSN2__FUNC_I2S2_MCK (MTK_PIN_NO(6) | 5) +#define MT8163_PIN_6_PWRAP_SPI0_CSN2__FUNC_I2S3_MCK (MTK_PIN_NO(6) | 6) +#define MT8163_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(6) | 7) + +#define MT8163_PIN_7_AUD_CLK_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8163_PIN_7_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(7) | 1) +#define MT8163_PIN_7_AUD_CLK_MOSI__FUNC_I2S2_BCK (MTK_PIN_NO(7) | 2) + +#define MT8163_PIN_8_AUD_DAT_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8163_PIN_8_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(8) | 1) +#define MT8163_PIN_8_AUD_DAT_MISO__FUNC_I2S2_DI (MTK_PIN_NO(8) | 2) +#define MT8163_PIN_8_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(8) | 3) + +#define MT8163_PIN_9_AUD_DAT_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8163_PIN_9_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(9) | 1) +#define MT8163_PIN_9_AUD_DAT_MOSI__FUNC_I2S2_LRCK (MTK_PIN_NO(9) | 2) +#define MT8163_PIN_9_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(9) | 3) + +#define MT8163_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8163_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) + +#define MT8163_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8163_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) + +#define MT8163_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8163_PIN_12_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(12) | 1) + +#define MT8163_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8163_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) + +#define MT8163_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8163_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1) +#define MT8163_PIN_14_URXD2__FUNC_DPI_D5 (MTK_PIN_NO(14) | 2) +#define MT8163_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 3) +#define MT8163_PIN_14_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(14) | 4) +#define MT8163_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) +#define MT8163_PIN_14_URXD2__FUNC_I2S0_MCK (MTK_PIN_NO(14) | 6) + +#define MT8163_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8163_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1) +#define MT8163_PIN_15_UTXD2__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 2) +#define MT8163_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 3) +#define MT8163_PIN_15_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(15) | 4) +#define MT8163_PIN_15_UTXD2__FUNC_I2S1_MCK (MTK_PIN_NO(15) | 6) + +#define MT8163_PIN_16_URXD3__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8163_PIN_16_URXD3__FUNC_URXD3 (MTK_PIN_NO(16) | 1) +#define MT8163_PIN_16_URXD3__FUNC_DPI_DE (MTK_PIN_NO(16) | 2) +#define MT8163_PIN_16_URXD3__FUNC_UTXD3 (MTK_PIN_NO(16) | 3) +#define MT8163_PIN_16_URXD3__FUNC_UCTS2 (MTK_PIN_NO(16) | 4) +#define MT8163_PIN_16_URXD3__FUNC_PWM_A (MTK_PIN_NO(16) | 5) +#define MT8163_PIN_16_URXD3__FUNC_I2S2_MCK (MTK_PIN_NO(16) | 6) +#define MT8163_PIN_16_URXD3__FUNC_TP_URXD3_AO (MTK_PIN_NO(16) | 7) + +#define MT8163_PIN_17_UTXD3__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8163_PIN_17_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(17) | 1) +#define MT8163_PIN_17_UTXD3__FUNC_DPI_VSYNC (MTK_PIN_NO(17) | 2) +#define MT8163_PIN_17_UTXD3__FUNC_URXD3 (MTK_PIN_NO(17) | 3) +#define MT8163_PIN_17_UTXD3__FUNC_URTS2 (MTK_PIN_NO(17) | 4) +#define MT8163_PIN_17_UTXD3__FUNC_PWM_B (MTK_PIN_NO(17) | 5) +#define MT8163_PIN_17_UTXD3__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6) +#define MT8163_PIN_17_UTXD3__FUNC_TP_UTXD3_AO (MTK_PIN_NO(17) | 7) + +#define MT8163_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8163_PIN_18_PCM_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(18) | 1) +#define MT8163_PIN_18_PCM_CLK__FUNC_DPI_D4 (MTK_PIN_NO(18) | 2) +#define MT8163_PIN_18_PCM_CLK__FUNC_I2S0_BCK0 (MTK_PIN_NO(18) | 3) +#define MT8163_PIN_18_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 4) +#define MT8163_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) +#define MT8163_PIN_18_PCM_CLK__FUNC_IR (MTK_PIN_NO(18) | 6) +#define MT8163_PIN_18_PCM_CLK__FUNC_DBG_MON_A_0 (MTK_PIN_NO(18) | 7) + +#define MT8163_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8163_PIN_19_PCM_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(19) | 1) +#define MT8163_PIN_19_PCM_SYNC__FUNC_DPI_D3 (MTK_PIN_NO(19) | 2) +#define MT8163_PIN_19_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(19) | 3) +#define MT8163_PIN_19_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 4) +#define MT8163_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) +#define MT8163_PIN_19_PCM_SYNC__FUNC_EXT_COL (MTK_PIN_NO(19) | 6) +#define MT8163_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_1 (MTK_PIN_NO(19) | 7) + +#define MT8163_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8163_PIN_20_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(20) | 1) +#define MT8163_PIN_20_PCM_RX__FUNC_DPI_D1 (MTK_PIN_NO(20) | 2) +#define MT8163_PIN_20_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(20) | 3) +#define MT8163_PIN_20_PCM_RX__FUNC_PCM0_DO (MTK_PIN_NO(20) | 4) +#define MT8163_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) +#define MT8163_PIN_20_PCM_RX__FUNC_EXT_MDIO (MTK_PIN_NO(20) | 6) +#define MT8163_PIN_20_PCM_RX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(20) | 7) + +#define MT8163_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8163_PIN_21_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(21) | 1) +#define MT8163_PIN_21_PCM_TX__FUNC_DPI_D2 (MTK_PIN_NO(21) | 2) +#define MT8163_PIN_21_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(21) | 3) +#define MT8163_PIN_21_PCM_TX__FUNC_PCM0_DI (MTK_PIN_NO(21) | 4) +#define MT8163_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) +#define MT8163_PIN_21_PCM_TX__FUNC_EXT_MDC (MTK_PIN_NO(21) | 6) +#define MT8163_PIN_21_PCM_TX__FUNC_DBG_MON_A_3 (MTK_PIN_NO(21) | 7) + +#define MT8163_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8163_PIN_22_EINT0__FUNC_PWM_B (MTK_PIN_NO(22) | 1) +#define MT8163_PIN_22_EINT0__FUNC_DPI_CK (MTK_PIN_NO(22) | 2) +#define MT8163_PIN_22_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(22) | 4) +#define MT8163_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 5) +#define MT8163_PIN_22_EINT0__FUNC_DBG_MON_A_4 (MTK_PIN_NO(22) | 7) + +#define MT8163_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8163_PIN_23_EINT1__FUNC_PWM_C (MTK_PIN_NO(23) | 1) +#define MT8163_PIN_23_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(23) | 2) +#define MT8163_PIN_23_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(23) | 4) +#define MT8163_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 5) +#define MT8163_PIN_23_EINT1__FUNC_DBG_MON_A_5 (MTK_PIN_NO(23) | 7) + +#define MT8163_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8163_PIN_24_EINT2__FUNC_CLKM0 (MTK_PIN_NO(24) | 1) +#define MT8163_PIN_24_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(24) | 2) +#define MT8163_PIN_24_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(24) | 4) +#define MT8163_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 5) +#define MT8163_PIN_24_EINT2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(24) | 7) + +#define MT8163_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8163_PIN_25_EINT3__FUNC_CLKM1 (MTK_PIN_NO(25) | 1) +#define MT8163_PIN_25_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(25) | 2) +#define MT8163_PIN_25_EINT3__FUNC_SPI_MI (MTK_PIN_NO(25) | 3) +#define MT8163_PIN_25_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(25) | 4) +#define MT8163_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 5) +#define MT8163_PIN_25_EINT3__FUNC_DBG_MON_A_7 (MTK_PIN_NO(25) | 7) + +#define MT8163_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8163_PIN_26_EINT4__FUNC_CLKM2 (MTK_PIN_NO(26) | 1) +#define MT8163_PIN_26_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(26) | 2) +#define MT8163_PIN_26_EINT4__FUNC_SPI_MO (MTK_PIN_NO(26) | 3) +#define MT8163_PIN_26_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(26) | 4) +#define MT8163_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 5) +#define MT8163_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 6) +#define MT8163_PIN_26_EINT4__FUNC_DBG_MON_A_8 (MTK_PIN_NO(26) | 7) + +#define MT8163_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8163_PIN_27_EINT5__FUNC_UCTS2 (MTK_PIN_NO(27) | 1) +#define MT8163_PIN_27_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(27) | 2) +#define MT8163_PIN_27_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(27) | 3) +#define MT8163_PIN_27_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(27) | 4) +#define MT8163_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 5) +#define MT8163_PIN_27_EINT5__FUNC_DBG_MON_A_9 (MTK_PIN_NO(27) | 7) + +#define MT8163_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8163_PIN_28_EINT6__FUNC_URTS2 (MTK_PIN_NO(28) | 1) +#define MT8163_PIN_28_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(28) | 2) +#define MT8163_PIN_28_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(28) | 3) +#define MT8163_PIN_28_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(28) | 4) +#define MT8163_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 5) +#define MT8163_PIN_28_EINT6__FUNC_DBG_MON_A_10 (MTK_PIN_NO(28) | 7) + +#define MT8163_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8163_PIN_29_EINT7__FUNC_UCTS3 (MTK_PIN_NO(29) | 1) +#define MT8163_PIN_29_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(29) | 2) +#define MT8163_PIN_29_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(29) | 3) +#define MT8163_PIN_29_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(29) | 4) +#define MT8163_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 5) +#define MT8163_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 6) +#define MT8163_PIN_29_EINT7__FUNC_DBG_MON_A_11 (MTK_PIN_NO(29) | 7) + +#define MT8163_PIN_30_EINT8__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8163_PIN_30_EINT8__FUNC_URTS3 (MTK_PIN_NO(30) | 1) +#define MT8163_PIN_30_EINT8__FUNC_CLKM3 (MTK_PIN_NO(30) | 2) +#define MT8163_PIN_30_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(30) | 3) +#define MT8163_PIN_30_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(30) | 4) +#define MT8163_PIN_30_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(30) | 5) +#define MT8163_PIN_30_EINT8__FUNC_DPI_D7 (MTK_PIN_NO(30) | 6) +#define MT8163_PIN_30_EINT8__FUNC_DBG_MON_B_2 (MTK_PIN_NO(30) | 7) + +#define MT8163_PIN_31_EINT9__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8163_PIN_31_EINT9__FUNC_CLKM4 (MTK_PIN_NO(31) | 1) +#define MT8163_PIN_31_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(31) | 2) +#define MT8163_PIN_31_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(31) | 3) +#define MT8163_PIN_31_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(31) | 4) +#define MT8163_PIN_31_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(31) | 5) +#define MT8163_PIN_31_EINT9__FUNC_DPI_D8 (MTK_PIN_NO(31) | 6) +#define MT8163_PIN_31_EINT9__FUNC_DBG_MON_B_3 (MTK_PIN_NO(31) | 7) + +#define MT8163_PIN_32_EINT10__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8163_PIN_32_EINT10__FUNC_CLKM5 (MTK_PIN_NO(32) | 1) +#define MT8163_PIN_32_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(32) | 2) +#define MT8163_PIN_32_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(32) | 3) +#define MT8163_PIN_32_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(32) | 4) +#define MT8163_PIN_32_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(32) | 5) +#define MT8163_PIN_32_EINT10__FUNC_DPI_D9 (MTK_PIN_NO(32) | 6) +#define MT8163_PIN_32_EINT10__FUNC_DBG_MON_B_4 (MTK_PIN_NO(32) | 7) + +#define MT8163_PIN_33_KPROW0__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8163_PIN_33_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(33) | 1) +#define MT8163_PIN_33_KPROW0__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) +#define MT8163_PIN_33_KPROW0__FUNC_DBG_MON_A_12 (MTK_PIN_NO(33) | 7) + +#define MT8163_PIN_34_KPROW1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8163_PIN_34_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(34) | 1) +#define MT8163_PIN_34_KPROW1__FUNC_IDDIG (MTK_PIN_NO(34) | 2) +#define MT8163_PIN_34_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(34) | 3) +#define MT8163_PIN_34_KPROW1__FUNC_MFG_TEST_CK (MTK_PIN_NO(34) | 4) +#define MT8163_PIN_34_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(34) | 7) + +#define MT8163_PIN_35_KPROW2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8163_PIN_35_KPROW2__FUNC_KPROW2 (MTK_PIN_NO(35) | 1) +#define MT8163_PIN_35_KPROW2__FUNC_USB_DRVVBUS (MTK_PIN_NO(35) | 2) +#define MT8163_PIN_35_KPROW2__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(35) | 3) +#define MT8163_PIN_35_KPROW2__FUNC_CONN_TEST_CK (MTK_PIN_NO(35) | 4) +#define MT8163_PIN_35_KPROW2__FUNC_DBG_MON_B_6 (MTK_PIN_NO(35) | 7) + +#define MT8163_PIN_36_KPCOL0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8163_PIN_36_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(36) | 1) +#define MT8163_PIN_36_KPCOL0__FUNC_DBG_MON_A_13 (MTK_PIN_NO(36) | 7) + +#define MT8163_PIN_37_KPCOL1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8163_PIN_37_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(37) | 1) +#define MT8163_PIN_37_KPCOL1__FUNC_MD32_JTAG_TRST (MTK_PIN_NO(37) | 4) +#define MT8163_PIN_37_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(37) | 7) + +#define MT8163_PIN_38_KPCOL2__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8163_PIN_38_KPCOL2__FUNC_KPCOL2 (MTK_PIN_NO(38) | 1) +#define MT8163_PIN_38_KPCOL2__FUNC_IDDIG (MTK_PIN_NO(38) | 2) +#define MT8163_PIN_38_KPCOL2__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(38) | 3) +#define MT8163_PIN_38_KPCOL2__FUNC_DBG_MON_B_8 (MTK_PIN_NO(38) | 7) + +#define MT8163_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8163_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1) +#define MT8163_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) +#define MT8163_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) +#define MT8163_PIN_39_JTMS__FUNC_MD32_JTAG_TMS (MTK_PIN_NO(39) | 4) +#define MT8163_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 5) + +#define MT8163_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8163_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1) +#define MT8163_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) +#define MT8163_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) +#define MT8163_PIN_40_JTCK__FUNC_MD32_JTAG_TCK (MTK_PIN_NO(40) | 4) +#define MT8163_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 5) + +#define MT8163_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8163_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1) +#define MT8163_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) +#define MT8163_PIN_41_JTDI__FUNC_MD32_JTAG_TDI (MTK_PIN_NO(41) | 4) +#define MT8163_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 5) + +#define MT8163_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8163_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1) +#define MT8163_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) +#define MT8163_PIN_42_JTDO__FUNC_MD32_JTAG_TDO (MTK_PIN_NO(42) | 4) +#define MT8163_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 5) + +#define MT8163_PIN_43_EINT11__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8163_PIN_43_EINT11__FUNC_CLKM4 (MTK_PIN_NO(43) | 1) +#define MT8163_PIN_43_EINT11__FUNC_PWM_C (MTK_PIN_NO(43) | 2) +#define MT8163_PIN_43_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(43) | 4) +#define MT8163_PIN_43_EINT11__FUNC_DPI_D10 (MTK_PIN_NO(43) | 5) +#define MT8163_PIN_43_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(43) | 6) +#define MT8163_PIN_43_EINT11__FUNC_DBG_MON_B_9 (MTK_PIN_NO(43) | 7) + +#define MT8163_PIN_44_EINT12__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8163_PIN_44_EINT12__FUNC_CLKM5 (MTK_PIN_NO(44) | 1) +#define MT8163_PIN_44_EINT12__FUNC_PWM_A (MTK_PIN_NO(44) | 2) +#define MT8163_PIN_44_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(44) | 4) +#define MT8163_PIN_44_EINT12__FUNC_DPI_D11 (MTK_PIN_NO(44) | 5) +#define MT8163_PIN_44_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(44) | 6) +#define MT8163_PIN_44_EINT12__FUNC_DBG_MON_B_10 (MTK_PIN_NO(44) | 7) + +#define MT8163_PIN_45_EINT13__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8163_PIN_45_EINT13__FUNC_SFCS0 (MTK_PIN_NO(45) | 3) +#define MT8163_PIN_45_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(45) | 4) +#define MT8163_PIN_45_EINT13__FUNC_DPI_D0 (MTK_PIN_NO(45) | 5) +#define MT8163_PIN_45_EINT13__FUNC_SPDIF (MTK_PIN_NO(45) | 6) +#define MT8163_PIN_45_EINT13__FUNC_DBG_MON_B_11 (MTK_PIN_NO(45) | 7) + +#define MT8163_PIN_46_EINT14__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8163_PIN_46_EINT14__FUNC_TP_GPIO0_AO (MTK_PIN_NO(46) | 1) +#define MT8163_PIN_46_EINT14__FUNC_I2S1_DO (MTK_PIN_NO(46) | 2) +#define MT8163_PIN_46_EINT14__FUNC_SFWP_B (MTK_PIN_NO(46) | 3) +#define MT8163_PIN_46_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(46) | 4) +#define MT8163_PIN_46_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(46) | 5) +#define MT8163_PIN_46_EINT14__FUNC_NCLE (MTK_PIN_NO(46) | 6) +#define MT8163_PIN_46_EINT14__FUNC_DBG_MON_A_14 (MTK_PIN_NO(46) | 7) + +#define MT8163_PIN_47_EINT15__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8163_PIN_47_EINT15__FUNC_TP_GPIO1_AO (MTK_PIN_NO(47) | 1) +#define MT8163_PIN_47_EINT15__FUNC_I2S1_LRCK (MTK_PIN_NO(47) | 2) +#define MT8163_PIN_47_EINT15__FUNC_SFOUT (MTK_PIN_NO(47) | 3) +#define MT8163_PIN_47_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(47) | 4) +#define MT8163_PIN_47_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(47) | 5) +#define MT8163_PIN_47_EINT15__FUNC_NCEB1 (MTK_PIN_NO(47) | 6) +#define MT8163_PIN_47_EINT15__FUNC_DBG_MON_A_15 (MTK_PIN_NO(47) | 7) + +#define MT8163_PIN_48_EINT16__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8163_PIN_48_EINT16__FUNC_I2S1_BCK (MTK_PIN_NO(48) | 2) +#define MT8163_PIN_48_EINT16__FUNC_SFHOLD (MTK_PIN_NO(48) | 3) +#define MT8163_PIN_48_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(48) | 4) +#define MT8163_PIN_48_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(48) | 5) +#define MT8163_PIN_48_EINT16__FUNC_NCEB0 (MTK_PIN_NO(48) | 6) +#define MT8163_PIN_48_EINT16__FUNC_DBG_MON_A_16 (MTK_PIN_NO(48) | 7) + +#define MT8163_PIN_49_EINT17__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8163_PIN_49_EINT17__FUNC_UCTS0 (MTK_PIN_NO(49) | 1) +#define MT8163_PIN_49_EINT17__FUNC_SFIN (MTK_PIN_NO(49) | 2) +#define MT8163_PIN_49_EINT17__FUNC_CLKM0 (MTK_PIN_NO(49) | 3) +#define MT8163_PIN_49_EINT17__FUNC_IDDIG (MTK_PIN_NO(49) | 4) +#define MT8163_PIN_49_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(49) | 5) +#define MT8163_PIN_49_EINT17__FUNC_NREB (MTK_PIN_NO(49) | 6) +#define MT8163_PIN_49_EINT17__FUNC_DBG_MON_A_17 (MTK_PIN_NO(49) | 7) + +#define MT8163_PIN_50_EINT18__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8163_PIN_50_EINT18__FUNC_URTS0 (MTK_PIN_NO(50) | 1) +#define MT8163_PIN_50_EINT18__FUNC_CLKM3 (MTK_PIN_NO(50) | 2) +#define MT8163_PIN_50_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(50) | 3) +#define MT8163_PIN_50_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(50) | 4) +#define MT8163_PIN_50_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(50) | 5) +#define MT8163_PIN_50_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(50) | 6) +#define MT8163_PIN_50_EINT18__FUNC_DBG_MON_B_12 (MTK_PIN_NO(50) | 7) + +#define MT8163_PIN_51_EINT19__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8163_PIN_51_EINT19__FUNC_UCTS1 (MTK_PIN_NO(51) | 1) +#define MT8163_PIN_51_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(51) | 3) +#define MT8163_PIN_51_EINT19__FUNC_CLKM1 (MTK_PIN_NO(51) | 4) +#define MT8163_PIN_51_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(51) | 5) +#define MT8163_PIN_51_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(51) | 6) +#define MT8163_PIN_51_EINT19__FUNC_DBG_MON_B_13 (MTK_PIN_NO(51) | 7) + +#define MT8163_PIN_52_EINT20__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8163_PIN_52_EINT20__FUNC_URTS1 (MTK_PIN_NO(52) | 1) +#define MT8163_PIN_52_EINT20__FUNC_PCM1_DO (MTK_PIN_NO(52) | 2) +#define MT8163_PIN_52_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(52) | 3) +#define MT8163_PIN_52_EINT20__FUNC_CLKM2 (MTK_PIN_NO(52) | 4) +#define MT8163_PIN_52_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(52) | 5) +#define MT8163_PIN_52_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(52) | 6) +#define MT8163_PIN_52_EINT20__FUNC_DBG_MON_B_14 (MTK_PIN_NO(52) | 7) + +#define MT8163_PIN_53_SPI_CS__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8163_PIN_53_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(53) | 1) +#define MT8163_PIN_53_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(53) | 3) +#define MT8163_PIN_53_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(53) | 4) +#define MT8163_PIN_53_SPI_CS__FUNC_DBG_MON_B_15 (MTK_PIN_NO(53) | 7) + +#define MT8163_PIN_54_SPI_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8163_PIN_54_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(54) | 1) +#define MT8163_PIN_54_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(54) | 3) +#define MT8163_PIN_54_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(54) | 4) +#define MT8163_PIN_54_SPI_CK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(54) | 7) + +#define MT8163_PIN_55_SPI_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8163_PIN_55_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(55) | 1) +#define MT8163_PIN_55_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(55) | 2) +#define MT8163_PIN_55_SPI_MI__FUNC_I2S0_BCK1 (MTK_PIN_NO(55) | 3) +#define MT8163_PIN_55_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 4) +#define MT8163_PIN_55_SPI_MI__FUNC_DBG_MON_B_17 (MTK_PIN_NO(55) | 7) + +#define MT8163_PIN_56_SPI_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8163_PIN_56_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(56) | 1) +#define MT8163_PIN_56_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(56) | 2) +#define MT8163_PIN_56_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(56) | 3) +#define MT8163_PIN_56_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(56) | 4) +#define MT8163_PIN_56_SPI_MO__FUNC_DBG_MON_B_18 (MTK_PIN_NO(56) | 7) + +#define MT8163_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8163_PIN_57_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(57) | 1) + +#define MT8163_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8163_PIN_58_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(58) | 1) + +#define MT8163_PIN_59_DISP_PWM__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8163_PIN_59_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(59) | 1) +#define MT8163_PIN_59_DISP_PWM__FUNC_PWM_B (MTK_PIN_NO(59) | 2) +#define MT8163_PIN_59_DISP_PWM__FUNC_DBG_MON_A_18 (MTK_PIN_NO(59) | 7) + +#define MT8163_PIN_60_WB_RSTB__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8163_PIN_60_WB_RSTB__FUNC_WB_RSTB (MTK_PIN_NO(60) | 1) +#define MT8163_PIN_60_WB_RSTB__FUNC_DBG_MON_A_19 (MTK_PIN_NO(60) | 7) + +#define MT8163_PIN_61_F2W_DATA__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8163_PIN_61_F2W_DATA__FUNC_F2W_DATA (MTK_PIN_NO(61) | 1) +#define MT8163_PIN_61_F2W_DATA__FUNC_MRG_CLK (MTK_PIN_NO(61) | 2) +#define MT8163_PIN_61_F2W_DATA__FUNC_DBG_MON_A_20 (MTK_PIN_NO(61) | 7) + +#define MT8163_PIN_62_F2W_CLK__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8163_PIN_62_F2W_CLK__FUNC_F2W_CK (MTK_PIN_NO(62) | 1) +#define MT8163_PIN_62_F2W_CLK__FUNC_MRG_DI (MTK_PIN_NO(62) | 2) +#define MT8163_PIN_62_F2W_CLK__FUNC_DBG_MON_A_21 (MTK_PIN_NO(62) | 7) + +#define MT8163_PIN_63_WB_SCLK__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8163_PIN_63_WB_SCLK__FUNC_WB_SCLK (MTK_PIN_NO(63) | 1) +#define MT8163_PIN_63_WB_SCLK__FUNC_MRG_DO (MTK_PIN_NO(63) | 2) +#define MT8163_PIN_63_WB_SCLK__FUNC_DBG_MON_A_22 (MTK_PIN_NO(63) | 7) + +#define MT8163_PIN_64_WB_SDATA__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8163_PIN_64_WB_SDATA__FUNC_WB_SDATA (MTK_PIN_NO(64) | 1) +#define MT8163_PIN_64_WB_SDATA__FUNC_MRG_SYNC (MTK_PIN_NO(64) | 2) +#define MT8163_PIN_64_WB_SDATA__FUNC_DBG_MON_A_23 (MTK_PIN_NO(64) | 7) + +#define MT8163_PIN_65_WB_SEN__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8163_PIN_65_WB_SEN__FUNC_WB_SEN (MTK_PIN_NO(65) | 1) +#define MT8163_PIN_65_WB_SEN__FUNC_DBG_MON_A_24 (MTK_PIN_NO(65) | 7) + +#define MT8163_PIN_66_WB_CRTL0__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8163_PIN_66_WB_CRTL0__FUNC_WB_CRTL0 (MTK_PIN_NO(66) | 1) +#define MT8163_PIN_66_WB_CRTL0__FUNC_DFD_NTRST_XI (MTK_PIN_NO(66) | 2) +#define MT8163_PIN_66_WB_CRTL0__FUNC_DBG_MON_A_25 (MTK_PIN_NO(66) | 7) + +#define MT8163_PIN_67_WB_CRTL1__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8163_PIN_67_WB_CRTL1__FUNC_WB_CRTL1 (MTK_PIN_NO(67) | 1) +#define MT8163_PIN_67_WB_CRTL1__FUNC_DFD_TMS_XI (MTK_PIN_NO(67) | 2) +#define MT8163_PIN_67_WB_CRTL1__FUNC_DBG_MON_A_26 (MTK_PIN_NO(67) | 7) + +#define MT8163_PIN_68_WB_CRTL2__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8163_PIN_68_WB_CRTL2__FUNC_WB_CRTL2 (MTK_PIN_NO(68) | 1) +#define MT8163_PIN_68_WB_CRTL2__FUNC_DFD_TCK_XI (MTK_PIN_NO(68) | 2) +#define MT8163_PIN_68_WB_CRTL2__FUNC_DBG_MON_A_27 (MTK_PIN_NO(68) | 7) + +#define MT8163_PIN_69_WB_CRTL3__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8163_PIN_69_WB_CRTL3__FUNC_WB_CRTL3 (MTK_PIN_NO(69) | 1) +#define MT8163_PIN_69_WB_CRTL3__FUNC_DFD_TDI_XI (MTK_PIN_NO(69) | 2) +#define MT8163_PIN_69_WB_CRTL3__FUNC_DBG_MON_A_28 (MTK_PIN_NO(69) | 7) + +#define MT8163_PIN_70_WB_CRTL4__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8163_PIN_70_WB_CRTL4__FUNC_WB_CRTL4 (MTK_PIN_NO(70) | 1) +#define MT8163_PIN_70_WB_CRTL4__FUNC_DFD_TDO (MTK_PIN_NO(70) | 2) +#define MT8163_PIN_70_WB_CRTL4__FUNC_DBG_MON_A_29 (MTK_PIN_NO(70) | 7) + +#define MT8163_PIN_71_WB_CRTL5__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8163_PIN_71_WB_CRTL5__FUNC_WB_CRTL5 (MTK_PIN_NO(71) | 1) +#define MT8163_PIN_71_WB_CRTL5__FUNC_DBG_MON_A_30 (MTK_PIN_NO(71) | 7) + +#define MT8163_PIN_72_I2S_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8163_PIN_72_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(72) | 1) +#define MT8163_PIN_72_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(72) | 2) +#define MT8163_PIN_72_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(72) | 3) +#define MT8163_PIN_72_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(72) | 4) +#define MT8163_PIN_72_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(72) | 5) +#define MT8163_PIN_72_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(72) | 6) +#define MT8163_PIN_72_I2S_DATA_IN__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7) + +#define MT8163_PIN_73_I2S_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8163_PIN_73_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1) +#define MT8163_PIN_73_I2S_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(73) | 2) +#define MT8163_PIN_73_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 3) +#define MT8163_PIN_73_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(73) | 4) +#define MT8163_PIN_73_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(73) | 5) +#define MT8163_PIN_73_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(73) | 6) +#define MT8163_PIN_73_I2S_LRCK__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7) + +#define MT8163_PIN_74_I2S_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT8163_PIN_74_I2S_BCK__FUNC_I2S0_BCK2 (MTK_PIN_NO(74) | 1) +#define MT8163_PIN_74_I2S_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(74) | 2) +#define MT8163_PIN_74_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(74) | 3) +#define MT8163_PIN_74_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(74) | 4) +#define MT8163_PIN_74_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(74) | 5) +#define MT8163_PIN_74_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(74) | 6) +#define MT8163_PIN_74_I2S_BCK__FUNC_DBG_MON_B_21 (MTK_PIN_NO(74) | 7) + +#define MT8163_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT8163_PIN_75_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(75) | 1) + +#define MT8163_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT8163_PIN_76_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(76) | 1) + +#define MT8163_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT8163_PIN_77_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(77) | 1) +#define MT8163_PIN_77_SDA2__FUNC_PWM_B (MTK_PIN_NO(77) | 2) + +#define MT8163_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT8163_PIN_78_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(78) | 1) +#define MT8163_PIN_78_SCL2__FUNC_PWM_C (MTK_PIN_NO(78) | 2) + +#define MT8163_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT8163_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1) +#define MT8163_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2) +#define MT8163_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5) + +#define MT8163_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT8163_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1) +#define MT8163_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2) + +#define MT8163_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT8163_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1) +#define MT8163_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2) + +#define MT8163_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT8163_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1) +#define MT8163_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2) + +#define MT8163_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT8163_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1) +#define MT8163_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) +#define MT8163_PIN_83_LCM_RST__FUNC_DBG_MON_A_31 (MTK_PIN_NO(83) | 7) + +#define MT8163_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT8163_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1) +#define MT8163_PIN_84_DSI_TE__FUNC_DBG_MON_A_32 (MTK_PIN_NO(84) | 7) + +#define MT8163_PIN_85_MSDC2_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT8163_PIN_85_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(85) | 1) +#define MT8163_PIN_85_MSDC2_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(85) | 2) +#define MT8163_PIN_85_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(85) | 3) +#define MT8163_PIN_85_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(85) | 6) +#define MT8163_PIN_85_MSDC2_CMD__FUNC_DBG_MON_B_22 (MTK_PIN_NO(85) | 7) + +#define MT8163_PIN_86_MSDC2_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT8163_PIN_86_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(86) | 1) +#define MT8163_PIN_86_MSDC2_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(86) | 2) +#define MT8163_PIN_86_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(86) | 3) +#define MT8163_PIN_86_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(86) | 6) +#define MT8163_PIN_86_MSDC2_CLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(86) | 7) + +#define MT8163_PIN_87_MSDC2_DAT0__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT8163_PIN_87_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(87) | 1) +#define MT8163_PIN_87_MSDC2_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(87) | 2) +#define MT8163_PIN_87_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(87) | 5) +#define MT8163_PIN_87_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(87) | 6) +#define MT8163_PIN_87_MSDC2_DAT0__FUNC_DBG_MON_B_24 (MTK_PIN_NO(87) | 7) + +#define MT8163_PIN_88_MSDC2_DAT1__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT8163_PIN_88_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(88) | 1) +#define MT8163_PIN_88_MSDC2_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(88) | 2) +#define MT8163_PIN_88_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(88) | 3) +#define MT8163_PIN_88_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(88) | 4) +#define MT8163_PIN_88_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(88) | 5) +#define MT8163_PIN_88_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(88) | 6) +#define MT8163_PIN_88_MSDC2_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(88) | 7) + +#define MT8163_PIN_89_MSDC2_DAT2__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT8163_PIN_89_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(89) | 1) +#define MT8163_PIN_89_MSDC2_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(89) | 2) +#define MT8163_PIN_89_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(89) | 3) +#define MT8163_PIN_89_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(89) | 5) +#define MT8163_PIN_89_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(89) | 6) +#define MT8163_PIN_89_MSDC2_DAT2__FUNC_DBG_MON_B_26 (MTK_PIN_NO(89) | 7) + +#define MT8163_PIN_90_MSDC2_DAT3__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT8163_PIN_90_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(90) | 1) +#define MT8163_PIN_90_MSDC2_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(90) | 2) +#define MT8163_PIN_90_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(90) | 3) +#define MT8163_PIN_90_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(90) | 4) +#define MT8163_PIN_90_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(90) | 5) +#define MT8163_PIN_90_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(90) | 6) +#define MT8163_PIN_90_MSDC2_DAT3__FUNC_DBG_MON_B_27 (MTK_PIN_NO(90) | 7) + +#define MT8163_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0) +#define MT8163_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1) + +#define MT8163_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) +#define MT8163_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1) + +#define MT8163_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0) +#define MT8163_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1) + +#define MT8163_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0) +#define MT8163_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1) + +#define MT8163_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0) +#define MT8163_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1) + +#define MT8163_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0) +#define MT8163_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1) + +#define MT8163_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0) +#define MT8163_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1) + +#define MT8163_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0) +#define MT8163_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1) + +#define MT8163_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0) +#define MT8163_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1) + +#define MT8163_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0) +#define MT8163_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1) + +#define MT8163_PIN_101_RDN0__FUNC_GPI101 (MTK_PIN_NO(101) | 0) +#define MT8163_PIN_101_RDN0__FUNC_RDN0 (MTK_PIN_NO(101) | 1) + +#define MT8163_PIN_102_RDP0__FUNC_GPI102 (MTK_PIN_NO(102) | 0) +#define MT8163_PIN_102_RDP0__FUNC_RDP0 (MTK_PIN_NO(102) | 1) + +#define MT8163_PIN_103_RDN1__FUNC_GPI103 (MTK_PIN_NO(103) | 0) +#define MT8163_PIN_103_RDN1__FUNC_RDN1 (MTK_PIN_NO(103) | 1) + +#define MT8163_PIN_104_RDP1__FUNC_GPI104 (MTK_PIN_NO(104) | 0) +#define MT8163_PIN_104_RDP1__FUNC_RDP1 (MTK_PIN_NO(104) | 1) + +#define MT8163_PIN_105_RCN__FUNC_GPI105 (MTK_PIN_NO(105) | 0) +#define MT8163_PIN_105_RCN__FUNC_RCN (MTK_PIN_NO(105) | 1) + +#define MT8163_PIN_106_RCP__FUNC_GPI106 (MTK_PIN_NO(106) | 0) +#define MT8163_PIN_106_RCP__FUNC_RCP (MTK_PIN_NO(106) | 1) + +#define MT8163_PIN_107_RDN2__FUNC_GPI107 (MTK_PIN_NO(107) | 0) +#define MT8163_PIN_107_RDN2__FUNC_RDN2 (MTK_PIN_NO(107) | 1) +#define MT8163_PIN_107_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(107) | 2) + +#define MT8163_PIN_108_RDP2__FUNC_GPI108 (MTK_PIN_NO(108) | 0) +#define MT8163_PIN_108_RDP2__FUNC_RDP2 (MTK_PIN_NO(108) | 1) +#define MT8163_PIN_108_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(108) | 2) + +#define MT8163_PIN_109_RDN3__FUNC_GPI109 (MTK_PIN_NO(109) | 0) +#define MT8163_PIN_109_RDN3__FUNC_RDN3 (MTK_PIN_NO(109) | 1) +#define MT8163_PIN_109_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(109) | 2) + +#define MT8163_PIN_110_RDP3__FUNC_GPI110 (MTK_PIN_NO(110) | 0) +#define MT8163_PIN_110_RDP3__FUNC_RDP3 (MTK_PIN_NO(110) | 1) +#define MT8163_PIN_110_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(110) | 2) + +#define MT8163_PIN_111_RCN_A__FUNC_GPI111 (MTK_PIN_NO(111) | 0) +#define MT8163_PIN_111_RCN_A__FUNC_RCN_A (MTK_PIN_NO(111) | 1) +#define MT8163_PIN_111_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(111) | 2) + +#define MT8163_PIN_112_RCP_A__FUNC_GPI112 (MTK_PIN_NO(112) | 0) +#define MT8163_PIN_112_RCP_A__FUNC_RCP_A (MTK_PIN_NO(112) | 1) +#define MT8163_PIN_112_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(112) | 2) + +#define MT8163_PIN_113_RDN1_A__FUNC_GPI113 (MTK_PIN_NO(113) | 0) +#define MT8163_PIN_113_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(113) | 1) +#define MT8163_PIN_113_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(113) | 2) +#define MT8163_PIN_113_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(113) | 3) + +#define MT8163_PIN_114_RDP1_A__FUNC_GPI114 (MTK_PIN_NO(114) | 0) +#define MT8163_PIN_114_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(114) | 1) +#define MT8163_PIN_114_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(114) | 2) +#define MT8163_PIN_114_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(114) | 3) + +#define MT8163_PIN_115_RDN0_A__FUNC_GPI115 (MTK_PIN_NO(115) | 0) +#define MT8163_PIN_115_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(115) | 1) +#define MT8163_PIN_115_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(115) | 2) + +#define MT8163_PIN_116_RDP0_A__FUNC_GPI116 (MTK_PIN_NO(116) | 0) +#define MT8163_PIN_116_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(116) | 1) +#define MT8163_PIN_116_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(116) | 2) + +#define MT8163_PIN_117_CMDAT0__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8163_PIN_117_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(117) | 1) +#define MT8163_PIN_117_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(117) | 2) +#define MT8163_PIN_117_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(117) | 3) +#define MT8163_PIN_117_CMDAT0__FUNC_DBG_MON_B_28 (MTK_PIN_NO(117) | 7) + +#define MT8163_PIN_118_CMDAT1__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8163_PIN_118_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(118) | 1) +#define MT8163_PIN_118_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(118) | 2) +#define MT8163_PIN_118_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(118) | 3) +#define MT8163_PIN_118_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(118) | 4) +#define MT8163_PIN_118_CMDAT1__FUNC_DBG_MON_B_29 (MTK_PIN_NO(118) | 7) + +#define MT8163_PIN_119_CMMCLK__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8163_PIN_119_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(119) | 1) +#define MT8163_PIN_119_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(119) | 3) +#define MT8163_PIN_119_CMMCLK__FUNC_DBG_MON_B_30 (MTK_PIN_NO(119) | 7) + +#define MT8163_PIN_120_CMPCLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8163_PIN_120_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(120) | 1) +#define MT8163_PIN_120_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(120) | 2) +#define MT8163_PIN_120_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(120) | 3) +#define MT8163_PIN_120_CMPCLK__FUNC_DBG_MON_B_31 (MTK_PIN_NO(120) | 7) + +#define MT8163_PIN_121_MSDC1_CMD__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8163_PIN_121_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(121) | 1) + +#define MT8163_PIN_122_MSDC1_CLK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8163_PIN_122_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(122) | 1) +#define MT8163_PIN_122_MSDC1_CLK__FUNC_MD32_JTAG_TCK (MTK_PIN_NO(122) | 2) + +#define MT8163_PIN_123_MSDC1_DAT0__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8163_PIN_123_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(123) | 1) +#define MT8163_PIN_123_MSDC1_DAT0__FUNC_MD32_JTAG_TMS (MTK_PIN_NO(123) | 2) + +#define MT8163_PIN_124_MSDC1_DAT1__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8163_PIN_124_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(124) | 1) +#define MT8163_PIN_124_MSDC1_DAT1__FUNC_MD32_JTAG_TDI (MTK_PIN_NO(124) | 2) + +#define MT8163_PIN_125_MSDC1_DAT2__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT8163_PIN_125_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(125) | 1) +#define MT8163_PIN_125_MSDC1_DAT2__FUNC_MD32_JTAG_TDO (MTK_PIN_NO(125) | 2) + +#define MT8163_PIN_126_MSDC1_DAT3__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT8163_PIN_126_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(126) | 1) +#define MT8163_PIN_126_MSDC1_DAT3__FUNC_MD32_JTAG_TRST (MTK_PIN_NO(126) | 2) + +#define MT8163_PIN_127_MSDC0_DAT7__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT8163_PIN_127_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(127) | 1) +#define MT8163_PIN_127_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(127) | 4) + +#define MT8163_PIN_128_MSDC0_DAT6__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT8163_PIN_128_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(128) | 1) +#define MT8163_PIN_128_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(128) | 4) + +#define MT8163_PIN_129_MSDC0_DAT5__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT8163_PIN_129_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1) +#define MT8163_PIN_129_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(129) | 4) + +#define MT8163_PIN_130_MSDC0_DAT4__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT8163_PIN_130_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(130) | 1) +#define MT8163_PIN_130_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(130) | 4) + +#define MT8163_PIN_131_MSDC0_RSTB__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT8163_PIN_131_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(131) | 1) +#define MT8163_PIN_131_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(131) | 4) + +#define MT8163_PIN_132_MSDC0_CMD__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT8163_PIN_132_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(132) | 1) +#define MT8163_PIN_132_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(132) | 4) + +#define MT8163_PIN_133_MSDC0_CLK__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT8163_PIN_133_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(133) | 1) +#define MT8163_PIN_133_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(133) | 4) + +#define MT8163_PIN_134_MSDC0_DAT3__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT8163_PIN_134_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(134) | 1) +#define MT8163_PIN_134_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(134) | 4) + +#define MT8163_PIN_135_MSDC0_DAT2__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT8163_PIN_135_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(135) | 1) +#define MT8163_PIN_135_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(135) | 4) + +#define MT8163_PIN_136_MSDC0_DAT1__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT8163_PIN_136_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(136) | 1) +#define MT8163_PIN_136_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(136) | 4) + +#define MT8163_PIN_137_MSDC0_DAT0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT8163_PIN_137_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(137) | 1) +#define MT8163_PIN_137_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(137) | 4) +#define MT8163_PIN_137_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(137) | 5) + +#define MT8163_PIN_138_CEC__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT8163_PIN_138_CEC__FUNC_CEC (MTK_PIN_NO(138) | 1) + +#define MT8163_PIN_139_HTPLG__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT8163_PIN_139_HTPLG__FUNC_HTPLG (MTK_PIN_NO(139) | 1) + +#define MT8163_PIN_140_HDMISCK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT8163_PIN_140_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(140) | 1) + +#define MT8163_PIN_141_HDMISD__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT8163_PIN_141_HDMISD__FUNC_HDMISD (MTK_PIN_NO(141) | 1) + +#define MT8163_PIN_142_EINT21__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT8163_PIN_142_EINT21__FUNC_NRNB (MTK_PIN_NO(142) | 1) +#define MT8163_PIN_142_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(142) | 2) +#define MT8163_PIN_142_EINT21__FUNC_SFCK (MTK_PIN_NO(142) | 3) +#define MT8163_PIN_142_EINT21__FUNC_DBG_MON_B_32 (MTK_PIN_NO(142) | 7) + +#define MT8163_PIN_143_MSDC3_DAT7__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT8163_PIN_143_MSDC3_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(143) | 1) + +#define MT8163_PIN_144_MSDC3_DAT6__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT8163_PIN_144_MSDC3_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(144) | 1) + +#define MT8163_PIN_145_MSDC3_DAT5__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define MT8163_PIN_145_MSDC3_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(145) | 1) + +#define MT8163_PIN_146_MSDC3_DAT4__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define MT8163_PIN_146_MSDC3_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(146) | 1) + +#define MT8163_PIN_147_MSDC3_RSTB__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define MT8163_PIN_147_MSDC3_RSTB__FUNC_MSDC3_RSTB (MTK_PIN_NO(147) | 1) + +#define MT8163_PIN_148_MSDC3_CMD__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define MT8163_PIN_148_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(148) | 1) + +#define MT8163_PIN_149_MSDC3_CLK__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define MT8163_PIN_149_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(149) | 1) + +#define MT8163_PIN_150_MSDC3_DAT3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define MT8163_PIN_150_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(150) | 1) + +#define MT8163_PIN_151_MSDC3_DAT2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define MT8163_PIN_151_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(151) | 1) + +#define MT8163_PIN_152_MSDC3_DAT1__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define MT8163_PIN_152_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(152) | 1) + +#define MT8163_PIN_153_MSDC3_DAT0__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define MT8163_PIN_153_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(153) | 1) + +#define MT8163_PIN_154_MSDC3_DSL__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define MT8163_PIN_154_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(154) | 1) + +#endif /* __DTS_MT8163_PINFUNC_H */ From a3ab793edbd1bd1ce9b4ecc155478f63e6761968 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 20:45:18 +0100 Subject: [PATCH 016/126] pinctrl: mediatek: Add support for MT8163 Add support for pinctrl on the MT8163 SoC. Signed-off-by: Ben Grisdale --- drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8163.c | 352 ++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt8163.h | 1445 +++++++++++++++++ 4 files changed, 1805 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8163.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8163.h diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 4819617d936836..6e461f5cf182f1 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -229,6 +229,13 @@ config PINCTRL_MT7988 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE +config PINCTRL_MT8163 + bool "MediaTek MT8163 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK + config PINCTRL_MT8167 bool "MediaTek MT8167 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index ae765bd999657c..c6a06056cb9bad 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o +obj-$(CONFIG_PINCTRL_MT8163) += pinctrl-mt8163.o obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8163.c b/drivers/pinctrl/mediatek/pinctrl-mt8163.c new file mode 100644 index 00000000000000..3f800decb61f35 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8163.c @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hongzhou.Yang + * Yingjoe Chen + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt8163.h" + +static const struct mtk_drv_group_desc mt8163_drv_grp[] = { + /* 0E4E8SR 4/8/12/16 */ + MTK_DRV_GRP(4, 16, 1, 2, 4), + /* 0E2E4SR 2/4/6/8 */ + MTK_DRV_GRP(2, 8, 1, 2, 2), + /* E8E4E2 2/4/6/8/10/12/14/16 */ + MTK_DRV_GRP(2, 16, 0, 2, 2) +}; + +static const struct mtk_pin_drv_grp mt8163_pin_drv[] = { + MTK_PIN_DRV_GRP(0, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(1, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(2, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(3, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(4, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(5, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(6, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(7, 0xb00, 12, 1), + MTK_PIN_DRV_GRP(8, 0xb00, 12, 1), + MTK_PIN_DRV_GRP(9, 0xb00, 12, 1), + MTK_PIN_DRV_GRP(10, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(11, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(12, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(13, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(14, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(15, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(16, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(17, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(18, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(19, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(20, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(21, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(22, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(23, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(24, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(25, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(26, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(27, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(28, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(29, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(30, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(31, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(32, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(33, 0xb30, 4, 1), + MTK_PIN_DRV_GRP(34, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(35, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(36, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(37, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(38, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(39, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(40, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(41, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(42, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(43, 0xb40, 12, 0), + MTK_PIN_DRV_GRP(44, 0xb40, 12, 0), + MTK_PIN_DRV_GRP(45, 0xb40, 12, 0), + MTK_PIN_DRV_GRP(46, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(47, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(48, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(49, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(50, 0xb70, 0, 1), + MTK_PIN_DRV_GRP(51, 0xb70, 0, 1), + MTK_PIN_DRV_GRP(52, 0xb70, 0, 1), + MTK_PIN_DRV_GRP(53, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(54, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(55, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(56, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(59, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(60, 0xb40, 0, 1), + MTK_PIN_DRV_GRP(61, 0xb40, 0, 1), + MTK_PIN_DRV_GRP(62, 0xb40, 0, 1), + MTK_PIN_DRV_GRP(63, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(64, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(65, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(66, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(67, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(68, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(69, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(70, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(71, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(72, 0xb50, 4, 1), + MTK_PIN_DRV_GRP(73, 0xb50, 4, 1), + MTK_PIN_DRV_GRP(74, 0xb50, 4, 1), + MTK_PIN_DRV_GRP(79, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(80, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(81, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(82, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(83, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(84, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(85, 0xce0, 0, 2), + MTK_PIN_DRV_GRP(86, 0xcd0, 0, 2), + MTK_PIN_DRV_GRP(87, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(88, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(89, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(90, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(117, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(118, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(119, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(120, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(121, 0xc80, 0, 2), + MTK_PIN_DRV_GRP(122, 0xc70, 0, 2), + MTK_PIN_DRV_GRP(123, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(124, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(125, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(126, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(127, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(128, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(129, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(130, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(131, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(132, 0xc10, 0, 2), + MTK_PIN_DRV_GRP(133, 0xc00, 0, 2), + MTK_PIN_DRV_GRP(134, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(135, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(136, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(137, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(142, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(143, 0xf20, 0, 2), + MTK_PIN_DRV_GRP(144, 0xf20, 0, 2), + MTK_PIN_DRV_GRP(145, 0xf20, 0, 2), + MTK_PIN_DRV_GRP(146, 0xf20, 0, 2), + MTK_PIN_DRV_GRP(147, 0xf20, 0, 2), + MTK_PIN_DRV_GRP(148, 0xf10, 0, 2), + MTK_PIN_DRV_GRP(149, 0xf00, 0, 2), + MTK_PIN_DRV_GRP(150, 0xf20, 0, 2), + MTK_PIN_DRV_GRP(151, 0xf20, 0, 2), + MTK_PIN_DRV_GRP(152, 0xf20, 0, 2), + MTK_PIN_DRV_GRP(153, 0xf20, 0, 2), + MTK_PIN_DRV_GRP(154, 0xf20, 0, 2), +}; + +static const struct mtk_pin_spec_pupd_set_samereg mt8163_spec_pupd[] = { + MTK_PIN_PUPD_SPEC_SR(33, 0xd90, 2, 1, 0), /* KPROW0 */ + MTK_PIN_PUPD_SPEC_SR(34, 0xd90, 6, 5, 4), /* KPROW1 */ + MTK_PIN_PUPD_SPEC_SR(35, 0xd90, 10, 9, 8), /* KPROW2 */ + MTK_PIN_PUPD_SPEC_SR(36, 0xda0, 2, 1, 0), /* KPCOL0 */ + MTK_PIN_PUPD_SPEC_SR(37, 0xda0, 6, 5, 4), /* KPCOL1 */ + MTK_PIN_PUPD_SPEC_SR(38, 0xda0, 10, 9, 8), /* KPCOL2 */ + MTK_PIN_PUPD_SPEC_SR(46, 0xdb0, 2, 1, 0), /* EINT14 */ + MTK_PIN_PUPD_SPEC_SR(47, 0xdb0, 6, 5, 4), /* EINT15 */ + MTK_PIN_PUPD_SPEC_SR(48, 0xdb0, 10, 9, 8), /* EINT16 */ + MTK_PIN_PUPD_SPEC_SR(49, 0xdb0, 14, 13, 12), /* EINT17 */ + MTK_PIN_PUPD_SPEC_SR(85, 0xce0, 8, 9, 10), /* MSDC2_CMD */ + MTK_PIN_PUPD_SPEC_SR(86, 0xcd0, 8, 9, 10), /* MSDC2_CLK */ + MTK_PIN_PUPD_SPEC_SR(87, 0xd00, 0, 1, 2), /* MSDC2_DAT0 */ + MTK_PIN_PUPD_SPEC_SR(88, 0xd00, 4, 5, 6), /* MSDC2_DAT1 */ + MTK_PIN_PUPD_SPEC_SR(89, 0xd00, 8, 9, 10), /* MSDC2_DAT2 */ + MTK_PIN_PUPD_SPEC_SR(90, 0xd00, 12, 13, 14), /* MSDC2_DAT3 */ + MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 9, 10), /* MSDC1_CMD */ + MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 9, 10), /* MSDC1_CLK */ + MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 1, 2), /* MSDC1_DAT0 */ + MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 5, 6), /* MSDC1_DAT1 */ + MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 9, 10), /* MSDC1_DAT2 */ + MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 13, 14), /* MSDC1_DAT3 */ + MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 13, 14), /* MSDC0_DAT7 */ + MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 9, 10), /* MSDC0_DAT6 */ + MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 5, 6), /* MSDC0_DAT5 */ + MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 1, 2), /* MSDC0_DAT4 */ + MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 1, 2), /* MSDC0_RSTB */ + MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 9, 10), /* MSDC0_CMD */ + MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 9, 10), /* MSDC0_CLK */ + MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 13, 14), /* MSDC0_DAT3 */ + MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 9, 10), /* MSDC0_DAT2 */ + MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 5, 6), /* MSDC0_DAT1 */ + MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 1, 2), /* MSDC0_DAT0 */ + MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 1, 0), /* EINT21 */ + MTK_PIN_PUPD_SPEC_SR(143, 0xf40, 12, 13, 14), /* MSDC3_DAT7 */ + MTK_PIN_PUPD_SPEC_SR(144, 0xf40, 8, 9, 10), /* MSDC3_DAT6 */ + MTK_PIN_PUPD_SPEC_SR(145, 0xf40, 4, 5, 6), /* MSDC3_DAT5 */ + MTK_PIN_PUPD_SPEC_SR(146, 0xf40, 0, 1, 2), /* MSDC3_DAT4 */ + MTK_PIN_PUPD_SPEC_SR(147, 0xf50, 0, 1, 2), /* MSDC3_RSTB */ + MTK_PIN_PUPD_SPEC_SR(148, 0xf10, 8, 9, 10), /* MSDC3_CMD */ + MTK_PIN_PUPD_SPEC_SR(149, 0xf00, 8, 9, 10), /* MSDC3_CLK */ + MTK_PIN_PUPD_SPEC_SR(150, 0xf30, 12, 13, 14), /* MSDC3_DAT3 */ + MTK_PIN_PUPD_SPEC_SR(151, 0xf30, 8, 9, 10), /* MSDC3_DAT2 */ + MTK_PIN_PUPD_SPEC_SR(152, 0xf30, 4, 5, 6), /* MSDC3_DAT1 */ + MTK_PIN_PUPD_SPEC_SR(153, 0xf30, 0, 1, 2), /* MSDC3_DAT0 */ + MTK_PIN_PUPD_SPEC_SR(154, 0xf50, 4, 5, 6), /* MSDC3_DSL */ +}; + +static const struct mtk_pin_ies_smt_set mt8163_ies_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0), + MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1), + MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2), + MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11), + MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10), + MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11), + MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12), + MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13), + MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10), + MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14), + MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0), + MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2), + MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3), + MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4), + MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15), + MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1), + MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5), + MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6), + MTK_PIN_IES_SMT_SPEC(87, 87, 0xcf0, 4), + MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7), + MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4), + MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4), + MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4), + MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4), + MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4), + MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4), + MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4), + MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9), + MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13), + MTK_PIN_IES_SMT_SPEC(143, 147, 0xf20, 4), + MTK_PIN_IES_SMT_SPEC(148, 148, 0xf10, 4), + MTK_PIN_IES_SMT_SPEC(149, 149, 0xf00, 4), + MTK_PIN_IES_SMT_SPEC(150, 153, 0xf20, 4), + MTK_PIN_IES_SMT_SPEC(154, 154, 0xf20, 7), +}; + +static const struct mtk_pin_ies_smt_set mt8163_smt_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0), + MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1), + MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2), + MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11), + MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10), + MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11), + MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12), + MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13), + MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10), + MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14), + MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0), + MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2), + MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3), + MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4), + MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15), + MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1), + MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5), + MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6), + MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11), + MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11), + MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3), + MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7), + MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11), + MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15), + MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7), + MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11), + MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11), + MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3), + MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7), + MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11), + MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15), + MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15), + MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11), + MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7), + MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3), + MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3), + MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11), + MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11), + MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15), + MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11), + MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7), + MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3), + MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9), + MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13), + MTK_PIN_IES_SMT_SPEC(143, 143, 0xf40, 15), + MTK_PIN_IES_SMT_SPEC(144, 144, 0xf40, 11), + MTK_PIN_IES_SMT_SPEC(145, 145, 0xf40, 7), + MTK_PIN_IES_SMT_SPEC(146, 146, 0xf40, 3), + MTK_PIN_IES_SMT_SPEC(147, 147, 0xf50, 3), + MTK_PIN_IES_SMT_SPEC(148, 148, 0xf10, 11), + MTK_PIN_IES_SMT_SPEC(149, 149, 0xf00, 11), + MTK_PIN_IES_SMT_SPEC(150, 150, 0xf30, 15), + MTK_PIN_IES_SMT_SPEC(151, 151, 0xf30, 11), + MTK_PIN_IES_SMT_SPEC(152, 152, 0xf30, 7), + MTK_PIN_IES_SMT_SPEC(153, 153, 0xf30, 3), + MTK_PIN_IES_SMT_SPEC(154, 154, 0xf50, 3), +}; + +static const struct mtk_pinctrl_devdata mt8163_pinctrl_data = { + .pins = mtk_pins_mt8163, + .npins = ARRAY_SIZE(mtk_pins_mt8163), + .grp_desc = mt8163_drv_grp, + .n_grp_cls = ARRAY_SIZE(mt8163_drv_grp), + .pin_drv_grp = mt8163_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt8163_pin_drv), + .spec_ies = mt8163_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8163_ies_set), + .spec_pupd = mt8163_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8163_spec_pupd), + .spec_smt = mt8163_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8163_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, + .dir_offset = 0x0000, + .pullen_offset = 0x0100, + .pullsel_offset = 0x0200, + .dout_offset = 0x0400, + .din_offset = 0x0500, + .pinmux_offset = 0x0600, + .type1_start = 155, + .type1_end = 155, + .port_shf = 4, + .port_mask = 0xf, + .port_align = 4, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, + .eint_hw = { + .port_mask = 7, + .ports = 6, + .ap_num = 169, + .db_cnt = 64, + .db_time = debounce_time_mt2701, + }, +}; + +static const struct of_device_id mt8163_pctrl_match[] = { + { .compatible = "mediatek,mt8163-pinctrl", .data = &mt8163_pinctrl_data }, + { } +}; + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mtk_pctrl_common_probe, + .driver = { + .name = "mediatek-mt8163-pinctrl", + .of_match_table = mt8163_pctrl_match, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} +arch_initcall(mtk_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8163.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8163.h new file mode 100644 index 00000000000000..143f5bdfee7722 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8163.h @@ -0,0 +1,1445 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 MediaTek Inc. + */ +#ifndef __PINCTRL_MTK_MT8163_H +#define __PINCTRL_MTK_MT8163_H + +#include +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt8163[] = { + MTK_PIN( + PINCTRL_PIN(0, "PWRAP_SPI0_MI"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 22), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + MTK_PIN( + PINCTRL_PIN(1, "PWRAP_SPI0_MO"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 23), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + MTK_PIN( + PINCTRL_PIN(2, "PWRAP_INT"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 24), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(4, "I2S1_MCK"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "I2S3_MCK") + ), + MTK_PIN( + PINCTRL_PIN(3, "PWRAP_SPI0_CK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 25), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + MTK_PIN( + PINCTRL_PIN(4, "PWRAP_SPI0_CSN"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 26), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + MTK_PIN( + PINCTRL_PIN(5, "PWRAP_SPI0_CK2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 27), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "ANT_SEL1"), + MTK_FUNCTION(3, "VDEC_TEST_CK"), + MTK_FUNCTION(4, "I2S1_MCK"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "I2S3_MCK"), + MTK_FUNCTION(7, "DBG_MON_B[0]") + ), + MTK_PIN( + PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 28), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(3, "MM_TEST_CK"), + MTK_FUNCTION(4, "I2S1_MCK"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "I2S3_MCK"), + MTK_FUNCTION(7, "DBG_MON_B[1]") + ), + MTK_PIN( + PINCTRL_PIN(7, "AUD_CLK_MOSI"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 29), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(2, "I2S2_BCK") + ), + MTK_PIN( + PINCTRL_PIN(8, "AUD_DAT_MISO"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 30), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "AUD_DAT_MISO"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "AUD_DAT_MOSI") + ), + MTK_PIN( + PINCTRL_PIN(9, "AUD_DAT_MOSI"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 31), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "AUD_DAT_MOSI"), + MTK_FUNCTION(2, "I2S2_LRCK"), + MTK_FUNCTION(3, "AUD_DAT_MISO") + ), + MTK_PIN( + PINCTRL_PIN(10, "RTC32K_CK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 32), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + PINCTRL_PIN(11, "WATCHDOG"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 33), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + PINCTRL_PIN(12, "SRCLKENA"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 34), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + PINCTRL_PIN(13, "SRCLKENAI"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 35), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "SRCLKENAI") + ), + MTK_PIN( + PINCTRL_PIN(14, "URXD2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 36), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "DPI_D5"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "DBG_SCL"), + MTK_FUNCTION(5, "SRCCLKENAI2"), + MTK_FUNCTION(6, "I2S0_MCK") + ), + MTK_PIN( + PINCTRL_PIN(15, "UTXD2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 37), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "DPI_HSYNC"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "DBG_SDA"), + MTK_FUNCTION(6, "I2S1_MCK") + ), + MTK_PIN( + PINCTRL_PIN(16, "URXD3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 38), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "URXD3"), + MTK_FUNCTION(2, "DPI_DE"), + MTK_FUNCTION(3, "UTXD3"), + MTK_FUNCTION(4, "UCTS2"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(6, "I2S2_MCK"), + MTK_FUNCTION(7, "TP_URXD3_AO") + ), + MTK_PIN( + PINCTRL_PIN(17, "UTXD3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 39), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "UTXD3"), + MTK_FUNCTION(2, "DPI_VSYNC"), + MTK_FUNCTION(3, "URXD3"), + MTK_FUNCTION(4, "URTS2"), + MTK_FUNCTION(5, "PWM_B"), + MTK_FUNCTION(6, "I2S3_MCK"), + MTK_FUNCTION(7, "TP_UTXD3_AO") + ), + MTK_PIN( + PINCTRL_PIN(18, "PCM_CLK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 40), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "PCM0_CLK"), + MTK_FUNCTION(2, "DPI_D4"), + MTK_FUNCTION(3, "I2S0_BCK0"), + MTK_FUNCTION(4, "I2S3_BCK"), + MTK_FUNCTION(5, "CONN_DSP_JCK"), + MTK_FUNCTION(6, "IR"), + MTK_FUNCTION(7, "DBG_MON_A[0]") + ), + MTK_PIN( + PINCTRL_PIN(19, "PCM_SYNC"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 41), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "PCM0_SYNC"), + MTK_FUNCTION(2, "DPI_D3"), + MTK_FUNCTION(3, "I2S0_LRCK"), + MTK_FUNCTION(4, "I2S3_LRCK"), + MTK_FUNCTION(5, "CONN_DSP_JINTP"), + MTK_FUNCTION(6, "EXT_COL"), + MTK_FUNCTION(7, "DBG_MON_A[1]") + ), + MTK_PIN( + PINCTRL_PIN(20, "PCM_RX"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 42), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "PCM0_DI"), + MTK_FUNCTION(2, "DPI_D1"), + MTK_FUNCTION(3, "I2S0_DI"), + MTK_FUNCTION(4, "PCM0_DO"), + MTK_FUNCTION(5, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "EXT_MDIO"), + MTK_FUNCTION(7, "DBG_MON_A[2]") + ), + MTK_PIN( + PINCTRL_PIN(21, "PCM_TX"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 43), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "PCM0_DO"), + MTK_FUNCTION(2, "DPI_D2"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "PCM0_DI"), + MTK_FUNCTION(5, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "EXT_MDC"), + MTK_FUNCTION(7, "DBG_MON_A[3]") + ), + MTK_PIN( + PINCTRL_PIN(22, "EINT0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 0), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "PWM_B"), + MTK_FUNCTION(2, "DPI_CK"), + MTK_FUNCTION(4, "EXT_TXD0"), + MTK_FUNCTION(5, "CONN_DSP_JDO"), + MTK_FUNCTION(7, "DBG_MON_A[4]") + ), + MTK_PIN( + PINCTRL_PIN(23, "EINT1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 1), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "PWM_C"), + MTK_FUNCTION(2, "DPI_D12"), + MTK_FUNCTION(4, "EXT_TXD1"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(7, "DBG_MON_A[5]") + ), + MTK_PIN( + PINCTRL_PIN(24, "EINT2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 2), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "CLKM0"), + MTK_FUNCTION(2, "DPI_D13"), + MTK_FUNCTION(4, "EXT_TXD2"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(7, "DBG_MON_A[6]") + ), + MTK_PIN( + PINCTRL_PIN(25, "EINT3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 3), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "CLKM1"), + MTK_FUNCTION(2, "DPI_D14"), + MTK_FUNCTION(3, "SPI_MI"), + MTK_FUNCTION(4, "EXT_TXD3"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(7, "DBG_MON_A[7]") + ), + MTK_PIN( + PINCTRL_PIN(26, "EINT4"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 4), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "CLKM2"), + MTK_FUNCTION(2, "DPI_D15"), + MTK_FUNCTION(3, "SPI_MO"), + MTK_FUNCTION(4, "EXT_TXC"), + MTK_FUNCTION(5, "CONN_MCU_TCK0"), + MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"), + MTK_FUNCTION(7, "DBG_MON_A[8]") + ), + MTK_PIN( + PINCTRL_PIN(27, "EINT5"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 5), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "UCTS2"), + MTK_FUNCTION(2, "DPI_D16"), + MTK_FUNCTION(3, "SPI_CSB"), + MTK_FUNCTION(4, "EXT_RXER"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(7, "DBG_MON_A[9]") + ), + MTK_PIN( + PINCTRL_PIN(28, "EINT6"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 6), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "URTS2"), + MTK_FUNCTION(2, "DPI_D17"), + MTK_FUNCTION(3, "SPI_CLK"), + MTK_FUNCTION(4, "EXT_RXC"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(7, "DBG_MON_A[10]") + ), + MTK_PIN( + PINCTRL_PIN(29, "EINT7"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 7), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "UCTS3"), + MTK_FUNCTION(2, "DPI_D6"), + MTK_FUNCTION(3, "SDA1_0"), + MTK_FUNCTION(4, "EXT_RXDV"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"), + MTK_FUNCTION(7, "DBG_MON_A[11]") + ), + MTK_PIN( + PINCTRL_PIN(30, "EINT8"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 8), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "URTS3"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "SCL1_0"), + MTK_FUNCTION(4, "EXT_RXD0"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "DPI_D7"), + MTK_FUNCTION(7, "DBG_MON_B[2]") + ), + MTK_PIN( + PINCTRL_PIN(31, "EINT9"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 9), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "CLKM4"), + MTK_FUNCTION(2, "SDA2_0"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "EXT_RXD1"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "DPI_D8"), + MTK_FUNCTION(7, "DBG_MON_B[3]") + ), + MTK_PIN( + PINCTRL_PIN(32, "EINT10"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 10), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "CLKM5"), + MTK_FUNCTION(2, "SCL2_0"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "EXT_RXD2"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "DPI_D9"), + MTK_FUNCTION(7, "DBG_MON_B[4]") + ), + MTK_PIN( + PINCTRL_PIN(33, "KPROW0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 44), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(4, "IMG_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A[12]") + ), + MTK_PIN( + PINCTRL_PIN(34, "KPROW1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 45), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "MFG_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[5]") + ), + MTK_PIN( + PINCTRL_PIN(35, "KPROW2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 46), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "KPROW2"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "CONN_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[6]") + ), + MTK_PIN( + PINCTRL_PIN(36, "KPCOL0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 47), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "KPCOL0"), + MTK_FUNCTION(7, "DBG_MON_A[13]") + ), + MTK_PIN( + PINCTRL_PIN(37, "KPCOL1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 48), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(4, "MD32_JTAG_TRST"), + MTK_FUNCTION(7, "DBG_MON_B[7]") + ), + MTK_PIN( + PINCTRL_PIN(38, "KPCOL2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 49), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "KPCOL2"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(7, "DBG_MON_B[8]") + ), + MTK_PIN( + PINCTRL_PIN(39, "JTMS"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 50), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "JTMS"), + MTK_FUNCTION(2, "CONN_MCU_TMS"), + MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC"), + MTK_FUNCTION(4, "MD32_JTAG_TMS"), + MTK_FUNCTION(5, "DFD_TMS_XI") + ), + MTK_PIN( + PINCTRL_PIN(40, "JTCK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 51), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "JTCK"), + MTK_FUNCTION(2, "CONN_MCU_TCK1"), + MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC"), + MTK_FUNCTION(4, "MD32_JTAG_TCK"), + MTK_FUNCTION(5, "DFD_TCK_XI") + ), + MTK_PIN( + PINCTRL_PIN(41, "JTDI"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 52), + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "JTDI"), + MTK_FUNCTION(2, "CONN_MCU_TDI"), + MTK_FUNCTION(4, "MD32_JTAG_TDI"), + MTK_FUNCTION(5, "DFD_TDI_XI") + ), + MTK_PIN( + PINCTRL_PIN(42, "JTDO"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 53), + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "JTDO"), + MTK_FUNCTION(2, "CONN_MCU_TDO"), + MTK_FUNCTION(4, "MD32_JTAG_TDO"), + MTK_FUNCTION(5, "DFD_TDO") + ), + MTK_PIN( + PINCTRL_PIN(43, "EINT11"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 11), + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "CLKM4"), + MTK_FUNCTION(2, "PWM_C"), + MTK_FUNCTION(4, "ANT_SEL3"), + MTK_FUNCTION(5, "DPI_D10"), + MTK_FUNCTION(6, "EXT_RXD3"), + MTK_FUNCTION(7, "DBG_MON_B[9]") + ), + MTK_PIN( + PINCTRL_PIN(44, "EINT12"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 12), + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "CLKM5"), + MTK_FUNCTION(2, "PWM_A"), + MTK_FUNCTION(4, "ANT_SEL4"), + MTK_FUNCTION(5, "DPI_D11"), + MTK_FUNCTION(6, "EXT_TXEN"), + MTK_FUNCTION(7, "DBG_MON_B[10]") + ), + MTK_PIN( + PINCTRL_PIN(45, "EINT13"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 13), + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(3, "SFCS0"), + MTK_FUNCTION(4, "ANT_SEL5"), + MTK_FUNCTION(5, "DPI_D0"), + MTK_FUNCTION(6, "SPDIF"), + MTK_FUNCTION(7, "DBG_MON_B[11]") + ), + MTK_PIN( + PINCTRL_PIN(46, "EINT14"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 14), + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "TP_GPIO0_AO"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "SFWP_B"), + MTK_FUNCTION(4, "ANT_SEL1"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "NCLE"), + MTK_FUNCTION(7, "DBG_MON_A[14]") + ), + MTK_PIN( + PINCTRL_PIN(47, "EINT15"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 15), + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "TP_GPIO1_AO"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(3, "SFOUT"), + MTK_FUNCTION(4, "ANT_SEL2"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "NCEB1"), + MTK_FUNCTION(7, "DBG_MON_A[15]") + ), + MTK_PIN( + PINCTRL_PIN(48, "EINT16"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 16), + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "SFHOLD"), + MTK_FUNCTION(4, "ANT_SEL3"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "NCEB0"), + MTK_FUNCTION(7, "DBG_MON_A[16]") + ), + MTK_PIN( + PINCTRL_PIN(49, "EINT17"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 17), + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "UCTS0"), + MTK_FUNCTION(2, "SFIN"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "IDDIG"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "NREB"), + MTK_FUNCTION(7, "DBG_MON_A[17]") + ), + MTK_PIN( + PINCTRL_PIN(50, "EINT18"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 18), + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "URTS0"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "USB_DRVVBUS"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_B[12]") + ), + MTK_PIN( + PINCTRL_PIN(51, "EINT19"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 19), + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "UCTS1"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "CLKM1"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_B[13]") + ), + MTK_PIN( + PINCTRL_PIN(52, "EINT20"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 20), + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "URTS1"), + MTK_FUNCTION(2, "PCM1_DO"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B[14]") + ), + MTK_PIN( + PINCTRL_PIN(53, "SPI_CS"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 54), + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "SPI_CSB"), + MTK_FUNCTION(3, "I2S0_DI"), + MTK_FUNCTION(4, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_B[15]") + ), + MTK_PIN( + PINCTRL_PIN(54, "SPI_CK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 55), + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "SPI_CLK"), + MTK_FUNCTION(3, "I2S0_LRCK"), + MTK_FUNCTION(4, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_B[16]") + ), + MTK_PIN( + PINCTRL_PIN(55, "SPI_MI"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 56), + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "SPI_MI"), + MTK_FUNCTION(2, "SPI_MO"), + MTK_FUNCTION(3, "I2S0_BCK1"), + MTK_FUNCTION(4, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B[17]") + ), + MTK_PIN( + PINCTRL_PIN(56, "SPI_MO"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 57), + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "SPI_MO"), + MTK_FUNCTION(2, "SPI_MI"), + MTK_FUNCTION(3, "I2S0_MCK"), + MTK_FUNCTION(4, "I2S2_MCK"), + MTK_FUNCTION(7, "DBG_MON_B[18]") + ), + MTK_PIN( + PINCTRL_PIN(57, "SDA1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 58), + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "SDA1_0") + ), + MTK_PIN( + PINCTRL_PIN(58, "SCL1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 59), + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SCL1_0") + ), + MTK_PIN( + PINCTRL_PIN(59, "DISP_PWM"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 60), + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM_B"), + MTK_FUNCTION(7, "DBG_MON_A[18]") + ), + MTK_PIN( + PINCTRL_PIN(60, "WB_RSTB"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 61), + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "WB_RSTB"), + MTK_FUNCTION(7, "DBG_MON_A[19]") + ), + MTK_PIN( + PINCTRL_PIN(61, "F2W_DATA"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 62), + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "F2W_DATA"), + MTK_FUNCTION(2, "MRG_CLK"), + MTK_FUNCTION(7, "DBG_MON_A[20]") + ), + MTK_PIN( + PINCTRL_PIN(62, "F2W_CLK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 63), + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "F2W_CK"), + MTK_FUNCTION(2, "MRG_DI"), + MTK_FUNCTION(7, "DBG_MON_A[21]") + ), + MTK_PIN( + PINCTRL_PIN(63, "WB_SCLK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 64), + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "WB_SCLK"), + MTK_FUNCTION(2, "MRG_DO"), + MTK_FUNCTION(7, "DBG_MON_A[22]") + ), + MTK_PIN( + PINCTRL_PIN(64, "WB_SDATA"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 65), + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "WB_SDATA"), + MTK_FUNCTION(2, "MRG_SYNC"), + MTK_FUNCTION(7, "DBG_MON_A[23]") + ), + MTK_PIN( + PINCTRL_PIN(65, "WB_SEN"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 66), + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "WB_SEN"), + MTK_FUNCTION(7, "DBG_MON_A[24]") + ), + MTK_PIN( + PINCTRL_PIN(66, "WB_CRTL0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 67), + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "WB_CRTL0"), + MTK_FUNCTION(2, "DFD_NTRST_XI"), + MTK_FUNCTION(7, "DBG_MON_A[25]") + ), + MTK_PIN( + PINCTRL_PIN(67, "WB_CRTL1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 68), + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "WB_CRTL1"), + MTK_FUNCTION(2, "DFD_TMS_XI"), + MTK_FUNCTION(7, "DBG_MON_A[26]") + ), + MTK_PIN( + PINCTRL_PIN(68, "WB_CRTL2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 69), + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "WB_CRTL2"), + MTK_FUNCTION(2, "DFD_TCK_XI"), + MTK_FUNCTION(7, "DBG_MON_A[27]") + ), + MTK_PIN( + PINCTRL_PIN(69, "WB_CRTL3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 70), + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "WB_CRTL3"), + MTK_FUNCTION(2, "DFD_TDI_XI"), + MTK_FUNCTION(7, "DBG_MON_A[28]") + ), + MTK_PIN( + PINCTRL_PIN(70, "WB_CRTL4"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 71), + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "WB_CRTL4"), + MTK_FUNCTION(2, "DFD_TDO"), + MTK_FUNCTION(7, "DBG_MON_A[29]") + ), + MTK_PIN( + PINCTRL_PIN(71, "WB_CRTL5"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 72), + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "WB_CRTL5"), + MTK_FUNCTION(7, "DBG_MON_A[30]") + ), + MTK_PIN( + PINCTRL_PIN(72, "I2S_DATA_IN"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 73), + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "PCM1_DI"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "I2S1_DO"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(6, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_B[19]") + ), + MTK_PIN( + PINCTRL_PIN(73, "I2S_LRCK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 74), + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "PCM1_SYNC"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "I2S1_LRCK"), + MTK_FUNCTION(5, "PWM_B"), + MTK_FUNCTION(6, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_B[20]") + ), + MTK_PIN( + PINCTRL_PIN(74, "I2S_BCK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 75), + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "I2S0_BCK2"), + MTK_FUNCTION(2, "PCM1_CLK"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "I2S1_BCK"), + MTK_FUNCTION(5, "PWM_C"), + MTK_FUNCTION(6, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B[21]") + ), + MTK_PIN( + PINCTRL_PIN(75, "SDA0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 76), + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SDA0_0") + ), + MTK_PIN( + PINCTRL_PIN(76, "SCL0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 77), + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "SCL0_0") + ), + MTK_PIN( + PINCTRL_PIN(77, "SDA2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 78), + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "SDA2_0"), + MTK_FUNCTION(2, "PWM_B") + ), + MTK_PIN( + PINCTRL_PIN(78, "SCL2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 79), + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "SCL2_0"), + MTK_FUNCTION(2, "PWM_C") + ), + MTK_PIN( + PINCTRL_PIN(79, "URXD0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 80), + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0"), + MTK_FUNCTION(5, " ") + ), + MTK_PIN( + PINCTRL_PIN(80, "UTXD0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 81), + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0") + ), + MTK_PIN( + PINCTRL_PIN(81, "URXD1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 82), + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "UTXD1") + ), + MTK_PIN( + PINCTRL_PIN(82, "UTXD1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 83), + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "URXD1") + ), + MTK_PIN( + PINCTRL_PIN(83, "LCM_RST"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 84), + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(2, "VDAC_CK_XI"), + MTK_FUNCTION(7, "DBG_MON_A[31]") + ), + MTK_PIN( + PINCTRL_PIN(84, "DSI_TE"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 85), + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "DBG_MON_A[32]") + ), + MTK_PIN( + PINCTRL_PIN(85, "MSDC2_CMD"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 86), + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(3, "SDA1_0"), + MTK_FUNCTION(6, "I2S3_BCK"), + MTK_FUNCTION(7, "DBG_MON_B[22]") + ), + MTK_PIN( + PINCTRL_PIN(86, "MSDC2_CLK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 87), + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "ANT_SEL1"), + MTK_FUNCTION(3, "SCL1_0"), + MTK_FUNCTION(6, "I2S3_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B[23]") + ), + MTK_PIN( + PINCTRL_PIN(87, "MSDC2_DAT0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 88), + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "ANT_SEL2"), + MTK_FUNCTION(5, "UTXD0"), + MTK_FUNCTION(6, "I2S3_DO"), + MTK_FUNCTION(7, "DBG_MON_B[24]") + ), + MTK_PIN( + PINCTRL_PIN(88, "MSDC2_DAT1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 89), + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "ANT_SEL3"), + MTK_FUNCTION(3, "PWM_A"), + MTK_FUNCTION(4, "I2S3_MCK"), + MTK_FUNCTION(5, "URXD0"), + MTK_FUNCTION(6, "PWM_B"), + MTK_FUNCTION(7, "DBG_MON_B[25]") + ), + MTK_PIN( + PINCTRL_PIN(89, "MSDC2_DAT2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 90), + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "ANT_SEL4"), + MTK_FUNCTION(3, "SDA2_0"), + MTK_FUNCTION(5, "UTXD1"), + MTK_FUNCTION(6, "PWM_C"), + MTK_FUNCTION(7, "DBG_MON_B[26]") + ), + MTK_PIN( + PINCTRL_PIN(90, "MSDC2_DAT3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 91), + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "ANT_SEL5"), + MTK_FUNCTION(3, "SCL2_0"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "URXD1"), + MTK_FUNCTION(6, "PWM_A"), + MTK_FUNCTION(7, "DBG_MON_B[27]") + ), + MTK_PIN( + PINCTRL_PIN(91, "TDN3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 92), + MTK_FUNCTION(0, "GPI91"), + MTK_FUNCTION(1, "TDN3") + ), + MTK_PIN( + PINCTRL_PIN(92, "TDP3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 93), + MTK_FUNCTION(0, "GPI92"), + MTK_FUNCTION(1, "TDP3") + ), + MTK_PIN( + PINCTRL_PIN(93, "TDN2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 94), + MTK_FUNCTION(0, "GPI93"), + MTK_FUNCTION(1, "TDN2") + ), + MTK_PIN( + PINCTRL_PIN(94, "TDP2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 95), + MTK_FUNCTION(0, "GPI94"), + MTK_FUNCTION(1, "TDP2") + ), + MTK_PIN( + PINCTRL_PIN(95, "TCN"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 96), + MTK_FUNCTION(0, "GPI95"), + MTK_FUNCTION(1, "TCN") + ), + MTK_PIN( + PINCTRL_PIN(96, "TCP"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 97), + MTK_FUNCTION(0, "GPI96"), + MTK_FUNCTION(1, "TCP") + ), + MTK_PIN( + PINCTRL_PIN(97, "TDN1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 98), + MTK_FUNCTION(0, "GPI97"), + MTK_FUNCTION(1, "TDN1") + ), + MTK_PIN( + PINCTRL_PIN(98, "TDP1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 99), + MTK_FUNCTION(0, "GPI98"), + MTK_FUNCTION(1, "TDP1") + ), + MTK_PIN( + PINCTRL_PIN(99, "TDN0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 100), + MTK_FUNCTION(0, "GPI99"), + MTK_FUNCTION(1, "TDN0") + ), + MTK_PIN( + PINCTRL_PIN(100, "TDP0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 101), + MTK_FUNCTION(0, "GPI100"), + MTK_FUNCTION(1, "TDP0") + ), + MTK_PIN( + PINCTRL_PIN(101, "RDN0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 102), + MTK_FUNCTION(0, "GPI101"), + MTK_FUNCTION(1, "RDN0") + ), + MTK_PIN( + PINCTRL_PIN(102, "RDP0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 103), + MTK_FUNCTION(0, "GPI102"), + MTK_FUNCTION(1, "RDP0") + ), + MTK_PIN( + PINCTRL_PIN(103, "RDN1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 104), + MTK_FUNCTION(0, "GPI103"), + MTK_FUNCTION(1, "RDN1") + ), + MTK_PIN( + PINCTRL_PIN(104, "RDP1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 105), + MTK_FUNCTION(0, "GPI104"), + MTK_FUNCTION(1, "RDP1") + ), + MTK_PIN( + PINCTRL_PIN(105, "RCN"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 106), + MTK_FUNCTION(0, "GPI105"), + MTK_FUNCTION(1, "RCN") + ), + MTK_PIN( + PINCTRL_PIN(106, "RCP"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 107), + MTK_FUNCTION(0, "GPI106"), + MTK_FUNCTION(1, "RCP") + ), + MTK_PIN( + PINCTRL_PIN(107, "RDN2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 108), + MTK_FUNCTION(0, "GPI107"), + MTK_FUNCTION(1, "RDN2"), + MTK_FUNCTION(2, "CMDAT8") + ), + MTK_PIN( + PINCTRL_PIN(108, "RDP2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 109), + MTK_FUNCTION(0, "GPI108"), + MTK_FUNCTION(1, "RDP2"), + MTK_FUNCTION(2, "CMDAT9") + ), + MTK_PIN( + PINCTRL_PIN(109, "RDN3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 110), + MTK_FUNCTION(0, "GPI109"), + MTK_FUNCTION(1, "RDN3"), + MTK_FUNCTION(2, "CMDAT4") + ), + MTK_PIN( + PINCTRL_PIN(110, "RDP3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 111), + MTK_FUNCTION(0, "GPI110"), + MTK_FUNCTION(1, "RDP3"), + MTK_FUNCTION(2, "CMDAT5") + ), + MTK_PIN( + PINCTRL_PIN(111, "RCN_A"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 112), + MTK_FUNCTION(0, "GPI111"), + MTK_FUNCTION(1, "RCN_A"), + MTK_FUNCTION(2, "CMDAT6") + ), + MTK_PIN( + PINCTRL_PIN(112, "RCP_A"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 113), + MTK_FUNCTION(0, "GPI112"), + MTK_FUNCTION(1, "RCP_A"), + MTK_FUNCTION(2, "CMDAT7") + ), + MTK_PIN( + PINCTRL_PIN(113, "RDN1_A"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 114), + MTK_FUNCTION(0, "GPI113"), + MTK_FUNCTION(1, "RDN1_A"), + MTK_FUNCTION(2, "CMDAT2"), + MTK_FUNCTION(3, "CMCSD2") + ), + MTK_PIN( + PINCTRL_PIN(114, "RDP1_A"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 115), + MTK_FUNCTION(0, "GPI114"), + MTK_FUNCTION(1, "RDP1_A"), + MTK_FUNCTION(2, "CMDAT3"), + MTK_FUNCTION(3, "CMCSD3") + ), + MTK_PIN( + PINCTRL_PIN(115, "RDN0_A"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 116), + MTK_FUNCTION(0, "GPI115"), + MTK_FUNCTION(1, "RDN0_A"), + MTK_FUNCTION(2, "CMHSYNC") + ), + MTK_PIN( + PINCTRL_PIN(116, "RDP0_A"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 117), + MTK_FUNCTION(0, "GPI116"), + MTK_FUNCTION(1, "RDP0_A"), + MTK_FUNCTION(2, "CMVSYNC") + ), + MTK_PIN( + PINCTRL_PIN(117, "CMDAT0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 118), + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(2, "CMCSD0"), + MTK_FUNCTION(3, "ANT_SEL2"), + MTK_FUNCTION(7, "DBG_MON_B[28]") + ), + MTK_PIN( + PINCTRL_PIN(118, "CMDAT1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 119), + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(2, "CMCSD1"), + MTK_FUNCTION(3, "ANT_SEL3"), + MTK_FUNCTION(4, "CMFLASH"), + MTK_FUNCTION(7, "DBG_MON_B[29]") + ), + MTK_PIN( + PINCTRL_PIN(119, "CMMCLK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 120), + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "CMMCLK"), + MTK_FUNCTION(3, "ANT_SEL4"), + MTK_FUNCTION(7, "DBG_MON_B[30]") + ), + MTK_PIN( + PINCTRL_PIN(120, "CMPCLK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 121), + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "CMCSK"), + MTK_FUNCTION(3, "ANT_SEL5"), + MTK_FUNCTION(7, "DBG_MON_B[31]") + ), + MTK_PIN( + PINCTRL_PIN(121, "MSDC1_CMD"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 122), + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "MSDC1_CMD") + ), + MTK_PIN( + PINCTRL_PIN(122, "MSDC1_CLK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 123), + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "MD32_JTAG_TCK") + ), + MTK_PIN( + PINCTRL_PIN(123, "MSDC1_DAT0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 124), + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "MD32_JTAG_TMS") + ), + MTK_PIN( + PINCTRL_PIN(124, "MSDC1_DAT1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 125), + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "MD32_JTAG_TDI") + ), + MTK_PIN( + PINCTRL_PIN(125, "MSDC1_DAT2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 126), + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "MD32_JTAG_TDO") + ), + MTK_PIN( + PINCTRL_PIN(126, "MSDC1_DAT3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 127), + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "MD32_JTAG_TRST") + ), + MTK_PIN( + PINCTRL_PIN(127, "MSDC0_DAT7"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 128), + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "MSDC0_DAT7"), + MTK_FUNCTION(4, "NLD7") + ), + MTK_PIN( + PINCTRL_PIN(128, "MSDC0_DAT6"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 129), + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "MSDC0_DAT6"), + MTK_FUNCTION(4, "NLD6") + ), + MTK_PIN( + PINCTRL_PIN(129, "MSDC0_DAT5"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 130), + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "MSDC0_DAT5"), + MTK_FUNCTION(4, "NLD4") + ), + MTK_PIN( + PINCTRL_PIN(130, "MSDC0_DAT4"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 131), + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "MSDC0_DAT4"), + MTK_FUNCTION(4, "NLD3") + ), + MTK_PIN( + PINCTRL_PIN(131, "MSDC0_RSTB"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 132), + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "MSDC0_RSTB"), + MTK_FUNCTION(4, "NLD0") + ), + MTK_PIN( + PINCTRL_PIN(132, "MSDC0_CMD"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 133), + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "MSDC0_CMD"), + MTK_FUNCTION(4, "NALE") + ), + MTK_PIN( + PINCTRL_PIN(133, "MSDC0_CLK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 134), + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(4, "NWEB") + ), + MTK_PIN( + PINCTRL_PIN(134, "MSDC0_DAT3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 135), + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "MSDC0_DAT3"), + MTK_FUNCTION(4, "NLD1") + ), + MTK_PIN( + PINCTRL_PIN(135, "MSDC0_DAT2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 136), + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "MSDC0_DAT2"), + MTK_FUNCTION(4, "NLD5") + ), + MTK_PIN( + PINCTRL_PIN(136, "MSDC0_DAT1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 137), + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "MSDC0_DAT1"), + MTK_FUNCTION(4, "NLD8") + ), + MTK_PIN( + PINCTRL_PIN(137, "MSDC0_DAT0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 138), + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "MSDC0_DAT0"), + MTK_FUNCTION(4, "WATCHDOG"), + MTK_FUNCTION(5, "NLD2") + ), + MTK_PIN( + PINCTRL_PIN(138, "CEC"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 139), + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "CEC") + ), + MTK_PIN( + PINCTRL_PIN(139, "HTPLG"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 140), + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "HTPLG") + ), + MTK_PIN( + PINCTRL_PIN(140, "HDMISCK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 141), + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "HDMISCK") + ), + MTK_PIN( + PINCTRL_PIN(141, "HDMISD"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 142), + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "HDMISD") + ), + MTK_PIN( + PINCTRL_PIN(142, "EINT21"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 21), + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "NRNB"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(3, "SFCK"), + MTK_FUNCTION(7, "DBG_MON_B[32]") + ), + MTK_PIN( + PINCTRL_PIN(143, "MSDC3_DAT7"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 143), + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "MSDC3_DAT7") + ), + MTK_PIN( + PINCTRL_PIN(144, "MSDC3_DAT6"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 144), + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "MSDC3_DAT6") + ), + MTK_PIN( + PINCTRL_PIN(145, "MSDC3_DAT5"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 145), + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "MSDC3_DAT5") + ), + MTK_PIN( + PINCTRL_PIN(146, "MSDC3_DAT4"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 146), + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "MSDC3_DAT4") + ), + MTK_PIN( + PINCTRL_PIN(147, "MSDC3_RSTB"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 147), + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "MSDC3_RSTB") + ), + MTK_PIN( + PINCTRL_PIN(148, "MSDC3_CMD"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 148), + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "MSDC3_CMD") + ), + MTK_PIN( + PINCTRL_PIN(149, "MSDC3_CLK"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 149), + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "MSDC3_CLK") + ), + MTK_PIN( + PINCTRL_PIN(150, "MSDC3_DAT3"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 150), + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "MSDC3_DAT3") + ), + MTK_PIN( + PINCTRL_PIN(151, "MSDC3_DAT2"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 151), + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "MSDC3_DAT2") + ), + MTK_PIN( + PINCTRL_PIN(152, "MSDC3_DAT1"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 152), + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "MSDC3_DAT1") + ), + MTK_PIN( + PINCTRL_PIN(153, "MSDC3_DAT0"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 153), + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "MSDC3_DAT0") + ), + MTK_PIN( + PINCTRL_PIN(154, "MSDC3_DSL"), + NULL, "mt8163", + MTK_EINT_FUNCTION(0, 154), + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "MSDC3_DSL") + ), +}; + +#endif /* __PINCTRL_MTK_MT8163_H */ From 3a4cebac87d1108077c2210a616d613a70540582 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 21:07:38 +0100 Subject: [PATCH 017/126] arm64: dts: mediatek: mt8163: Add pinctrl Add device tree nodes for pinctrl on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 518a982f960d53..c2cd646b5123d5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -144,6 +145,11 @@ #reset-cells = <1>; }; + syscfg_pctl_a: syscon@10005000 { + compatible = "mediatek,mt8163-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8163-wdt"; reg = <0 0x10007000 0 0x1000>; @@ -159,6 +165,19 @@ clock-names = "system-clk", "rtc-clk"; }; + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8163-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + ; + }; + apmixedsys: clock-controller@1000c000 { compatible = "mediatek,mt8163-apmixedsys"; reg = <0 0x1000c000 0 0x1000>; From 38b7eda8fdf0fc068bb4c64d5144f1888b64d81e Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 19:00:29 +0100 Subject: [PATCH 018/126] soc: mediatek: mtk-pmic-wrap: Add support for MT8163 Add support for the PMIC wrapper on the MT8163 SoC. Signed-off-by: Ben Grisdale --- drivers/soc/mediatek/mtk-pmic-wrap.c | 100 +++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 0bcd8582637550..019cd58d671bd4 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -954,6 +954,88 @@ static const int mt8135_regs[] = { [PWRAP_DCM_DBC_PRD] = 0x160, }; +static const int mt8163_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_SIDLY] = 0xc, + [PWRAP_RDDMY] = 0x10, + [PWRAP_SI_CK_CON] = 0x14, + [PWRAP_CSHEXT_WRITE] = 0x18, + [PWRAP_CSHEXT_READ] = 0x1c, + [PWRAP_CSLEXT_START] = 0x20, + [PWRAP_CSLEXT_END] = 0x24, + [PWRAP_STAUPD_PRD] = 0x28, + [PWRAP_STAUPD_GRPEN] = 0x2c, + [PWRAP_STAUPD_MAN_TRIG] = 0x40, + [PWRAP_STAUPD_STA] = 0x44, + [PWRAP_WRAP_STA] = 0x48, + [PWRAP_HARB_INIT] = 0x4c, + [PWRAP_HARB_HPRIO] = 0x50, + [PWRAP_HIPRIO_ARB_EN] = 0x54, + [PWRAP_HARB_STA0] = 0x58, + [PWRAP_HARB_STA1] = 0x5c, + [PWRAP_MAN_EN] = 0x60, + [PWRAP_MAN_CMD] = 0x64, + [PWRAP_MAN_RDATA] = 0x68, + [PWRAP_MAN_VLDCLR] = 0x6c, + [PWRAP_WACS0_EN] = 0x70, + [PWRAP_INIT_DONE0] = 0x74, + [PWRAP_WACS0_CMD] = 0x78, + [PWRAP_WACS0_RDATA] = 0x7c, + [PWRAP_WACS0_VLDCLR] = 0x80, + [PWRAP_WACS1_EN] = 0x84, + [PWRAP_INIT_DONE1] = 0x88, + [PWRAP_WACS1_CMD] = 0x8c, + [PWRAP_WACS1_RDATA] = 0x90, + [PWRAP_WACS1_VLDCLR] = 0x94, + [PWRAP_WACS2_EN] = 0x98, + [PWRAP_INIT_DONE2] = 0x9c, + [PWRAP_WACS2_CMD] = 0xa0, + [PWRAP_WACS2_RDATA] = 0xa4, + [PWRAP_WACS2_VLDCLR] = 0xa8, + [PWRAP_INT_EN] = 0xac, + [PWRAP_INT_FLG_RAW] = 0xb0, + [PWRAP_INT_FLG] = 0xb4, + [PWRAP_INT_CLR] = 0xb8, + [PWRAP_SIG_ADR] = 0xbc, + [PWRAP_SIG_MODE] = 0xc0, + [PWRAP_SIG_VALUE] = 0xc4, + [PWRAP_SIG_ERRVAL] = 0xc8, + [PWRAP_CRC_EN] = 0xcc, + [PWRAP_TIMER_EN] = 0xd0, + [PWRAP_TIMER_STA] = 0xd4, + [PWRAP_WDT_UNIT] = 0xd8, + [PWRAP_WDT_SRC_EN] = 0xdc, + [PWRAP_WDT_FLG] = 0xe0, + [PWRAP_DEBUG_INT_SEL] = 0xe4, + [PWRAP_DVFS_ADR0] = 0xe8, + [PWRAP_DVFS_WDATA0] = 0xec, + [PWRAP_DVFS_ADR1] = 0xf0, + [PWRAP_DVFS_WDATA1] = 0xf4, + [PWRAP_DVFS_ADR2] = 0xf8, + [PWRAP_DVFS_WDATA2] = 0xfc, + [PWRAP_DVFS_ADR3] = 0x100, + [PWRAP_DVFS_WDATA3] = 0x104, + [PWRAP_DVFS_ADR4] = 0x108, + [PWRAP_DVFS_WDATA4] = 0x10c, + [PWRAP_DVFS_ADR5] = 0x110, + [PWRAP_DVFS_WDATA5] = 0x114, + [PWRAP_DVFS_ADR6] = 0x118, + [PWRAP_DVFS_WDATA6] = 0x11c, + [PWRAP_DVFS_ADR7] = 0x120, + [PWRAP_DVFS_WDATA7] = 0x124, + [PWRAP_SPMINF_STA] = 0x128, + [PWRAP_CIPHER_KEY_SEL] = 0x12c, + [PWRAP_CIPHER_IV_SEL] = 0x130, + [PWRAP_CIPHER_EN] = 0x134, + [PWRAP_CIPHER_RDY] = 0x138, + [PWRAP_CIPHER_MODE] = 0x13c, + [PWRAP_CIPHER_SWRST] = 0x140, + [PWRAP_DCM_EN] = 0x144, + [PWRAP_DCM_DBC_PRD] = 0x148, +}; + static const int mt8173_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -1321,6 +1403,7 @@ enum pwrap_type { PWRAP_MT6873, PWRAP_MT7622, PWRAP_MT8135, + PWRAP_MT8163, PWRAP_MT8173, PWRAP_MT8183, PWRAP_MT8186, @@ -1843,6 +1926,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT6779: case PWRAP_MT6795: case PWRAP_MT6797: + case PWRAP_MT8163: case PWRAP_MT8173: case PWRAP_MT8186: case PWRAP_MT8365: @@ -2063,6 +2147,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) switch (wrp->master->type) { case PWRAP_MT6795: fallthrough; + case PWRAP_MT8163: + fallthrough; case PWRAP_MT8173: /* Enable DCM */ pwrap_writel(wrp, 3, PWRAP_DCM_EN); @@ -2367,6 +2453,19 @@ static const struct pmic_wrapper_type pwrap_mt8135 = { .init_soc_specific = pwrap_mt8135_init_soc_specific, }; +static const struct pmic_wrapper_type pwrap_mt8163 = { + .regs = mt8163_regs, + .type = PWRAP_MT8163, + .arb_en_all = 0xff, + .int_en_all = ~(u32)(BIT(31) | BIT(2)), + .int1_en_all = 0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .init_reg_clock = pwrap_mt2701_init_reg_clock, + .init_soc_specific = pwrap_mt2701_init_soc_specific, +}; + static const struct pmic_wrapper_type pwrap_mt8173 = { .regs = mt8173_regs, .type = PWRAP_MT8173, @@ -2453,6 +2552,7 @@ static const struct of_device_id of_pwrap_match_tbl[] = { { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 }, { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 }, { .compatible = "mediatek,mt8135-pwrap", .data = &pwrap_mt8135 }, + { .compatible = "mediatek,mt8163-pwrap", .data = &pwrap_mt8163 }, { .compatible = "mediatek,mt8173-pwrap", .data = &pwrap_mt8173 }, { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183 }, { .compatible = "mediatek,mt8186-pwrap", .data = &pwrap_mt8186 }, From 2d96f43ac4402c8cd0853d2a882642773888e482 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 20:08:43 +0100 Subject: [PATCH 019/126] arm64: dts: mediatek: mt8163: Add PWRAP Add PWRAP device node for the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index c2cd646b5123d5..3080fdcc89890f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -184,6 +184,17 @@ #clock-cells = <1>; }; + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8163-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + resets = <&infracfg MT8163_INFRA_RST1_PMIC_WRAP>; + reset-names = "pwrap"; + clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&infracfg CLK_INFRA_PMIC_AP>; + clock-names = "spi", "wrap"; + }; + sysirq: intpol-controller@10200620 { compatible = "mediatek,mt8163-sysirq", "mediatek,mt6577-sysirq"; reg = <0 0x10200620 0 0x20>; From 1dbc1788f04c8ae19b261a0e9d81e1bd812db6a5 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 20:09:22 +0100 Subject: [PATCH 020/126] arm64: dts: mediatek: Add device tree for MT6323 PMIC Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt6323.dtsi | 247 +++++++++++++++++++++++ 1 file changed, 247 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6323.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6323.dtsi b/arch/arm64/boot/dts/mediatek/mt6323.dtsi new file mode 100644 index 00000000000000..9cedd8d03d4afd --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6323.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018 MediaTek Inc. + * Author: John Crispin + * Sean Wang + * + */ + +&pwrap { + pmic: mt6323 { + compatible = "mediatek,mt6323"; + interrupt-controller; + #interrupt-cells = <2>; + + mt6323_leds: leds { + compatible = "mediatek,mt6323-led"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mt6323regulator: mt6323regulator { + compatible = "mediatek,mt6323-regulator"; + + mt6323_vproc_reg: buck_vproc { + regulator-name = "vproc"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + }; + + mt6323_vsys_reg: buck_vsys { + regulator-name = "vsys"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <2987500>; + regulator-ramp-delay = <25000>; + }; + + mt6323_vpa_reg: buck_vpa { + regulator-name = "vpa"; + regulator-min-microvolt = < 500000>; + regulator-max-microvolt = <3650000>; + }; + + mt6323_vtcxo_reg: ldo_vtcxo { + regulator-name = "vtcxo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <90>; + }; + + mt6323_vcn28_reg: ldo_vcn28 { + regulator-name = "vcn28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <185>; + }; + + mt6323_vcn33_bt_reg: ldo_vcn33_bt { + regulator-name = "vcn33_bt"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <185>; + }; + + mt6323_vcn33_wifi_reg: ldo_vcn33_wifi { + regulator-name = "vcn33_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <185>; + }; + + mt6323_va_reg: ldo_va { + regulator-name = "va"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vcama_reg: ldo_vcama { + regulator-name = "vcama"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vio28_reg: ldo_vio28 { + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vusb_reg: ldo_vusb { + regulator-name = "vusb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vmc_reg: ldo_vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <36>; + }; + + mt6323_vmch_reg: ldo_vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <36>; + }; + + mt6323_vemc3v3_reg: ldo_vemc3v3 { + regulator-name = "vemc3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <36>; + }; + + mt6323_vgp1_reg: ldo_vgp1 { + regulator-name = "vgp1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vgp2_reg: ldo_vgp2 { + regulator-name = "vgp2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vgp3_reg: ldo_vgp3 { + regulator-name = "vgp3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vcn18_reg: ldo_vcn18 { + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vsim1_reg: ldo_vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vsim2_reg: ldo_vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vrtc_reg: ldo_vrtc { + regulator-name = "vrtc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + mt6323_vcamaf_reg: ldo_vcamaf { + regulator-name = "vcamaf"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vibr_reg: ldo_vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <36>; + }; + + mt6323_vrf18_reg: ldo_vrf18 { + regulator-name = "vrf18"; + regulator-min-microvolt = <1825000>; + regulator-max-microvolt = <1825000>; + regulator-enable-ramp-delay = <187>; + }; + + mt6323_vm_reg: ldo_vm { + regulator-name = "vm"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vio18_reg: ldo_vio18 { + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vcamd_reg: ldo_vcamd { + regulator-name = "vcamd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + }; + + mt6323_vcamio_reg: ldo_vcamio { + regulator-name = "vcamio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <216>; + }; + }; + + mt6323keys: mt6323keys { + compatible = "mediatek,mt6323-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power { + linux,keycodes = <116>; + wakeup-source; + }; + + home { + linux,keycodes = <114>; + }; + }; + + codec: mt6397codec { + compatible = "mediatek,mt6397-codec"; + }; + + power-controller { + compatible = "mediatek,mt6323-pwrc"; + }; + + rtc { + compatible = "mediatek,mt6323-rtc"; + }; + }; +}; From 5adb54ef6bc82fa79fd8d07cad57a5afbe54bcd9 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 21:29:21 +0100 Subject: [PATCH 021/126] dt-bindings: dma: Add binding for MT8163 UART APDMA Add a devicetree binding for the UART APDMA controller on the MT8163 SoC. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml index 3708518fe7fc1a..e2b9ea210b8160 100644 --- a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml +++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml @@ -24,6 +24,7 @@ properties: - enum: - mediatek,mt2712-uart-dma - mediatek,mt6795-uart-dma + - mediatek,mt8163-uart-dma - mediatek,mt8173-uart-dma - mediatek,mt8183-uart-dma - mediatek,mt8365-uart-dma From 5ae08c373ab617777f2ef97ed3b7bba0a461283d Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 21:30:08 +0100 Subject: [PATCH 022/126] dt-bindings: serial: Add binding for MT8163 UART Add a devicetree binding for the UART controller on the MT8163 SoC. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml index 5bd8a8853ae0d4..11801b58f63752 100644 --- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml +++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml @@ -43,6 +43,7 @@ properties: - mediatek,mt7988-uart - mediatek,mt8127-uart - mediatek,mt8135-uart + - mediatek,mt8163-uart - mediatek,mt8173-uart - mediatek,mt8183-uart - mediatek,mt8186-uart From 0e00a2f1c847c3cab954f4602fba0237d55bfc0b Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 21:30:59 +0100 Subject: [PATCH 023/126] arm64: dts: mediatek: mt8163: Add UART Add device tree nodes for the UART APDMA and 3 UART controllers on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 3080fdcc89890f..f7091f8b1138be 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -250,5 +250,73 @@ ; }; }; + + apdma: dma-controller@11000300 { + compatible = "mediatek,mt8163-uart-dma", "mediatek,mt6577-uart-dma"; + reg = <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000480 0 0x80>, + <0 0x11000500 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>, + <0 0x11000680 0 0x80>; + interrupts = , + , + , + , + , + , + , + ; + dma-requests = <8>; + clocks = <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8163-uart", "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + dmas = <&apdma 0 &apdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8163-uart", "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2 &apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8163-uart", "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4 &apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt8163-uart", "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART3>; + clock-names = "baud", "bus"; + dmas = <&apdma 6 &apdma 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; }; From 4f6dd4cc742a69bdef34878c5a99e93a6851667b Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 30 Aug 2025 23:59:42 +0100 Subject: [PATCH 024/126] dt-bindings: mmc: Add binding for MediaTek MT8163 MSDC Add a devicetree binding for the MMC controller (MSDC) found on the MediaTek MT8163 SoC. The MSDC IP is similar to that of MT2701, so the existing binding is reused. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index eb3755bdfdf7e0..343d45baca29d9 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -29,7 +29,9 @@ properties: - mediatek,mt8196-mmc - mediatek,mt8516-mmc - items: - - const: mediatek,mt7623-mmc + - enum: + - mediatek,mt7623-mmc + - mediatek,mt8163-mmc - const: mediatek,mt2701-mmc - items: - enum: From f97b31dde04d973908dc940670f36c3916dcd1ec Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 00:09:11 +0100 Subject: [PATCH 025/126] arm64: dts: mediatek: mt8163: Add MMC controllers Add devicetree nodes for the two MMC controllers found on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 31 ++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index f7091f8b1138be..854f5bb2343aac 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -318,5 +318,36 @@ dma-names = "tx", "rx"; status = "disabled"; }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8163-mmc", "mediatek,mt2701-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC0>, + <&topckgen CLK_TOP_MSDC30_0_SEL>, + <&infracfg CLK_INFRA_MSDC3>; + clock-names = "source", "hclk", "bus_clk"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8163-mmc", "mediatek,mt2701-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC1>, + <&topckgen CLK_TOP_MSDC30_1_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt8163-mmc", "mediatek,mt2701-mmc"; + reg = <0 0x11250000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC2>, + <&topckgen CLK_TOP_MSDC30_2_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; }; }; From a9e0ea9b583ca73958a185b4fcdc2877120562b2 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 13:05:22 +0100 Subject: [PATCH 026/126] dt-bindings: phy: Add binding for MT8163 T-PHY Add a devicetree binding for the T-PHY on the MT8163 SoC. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index ff5c77ef11765c..6ca595ce282010 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -73,6 +73,7 @@ properties: - mediatek,mt2701-tphy - mediatek,mt7623-tphy - mediatek,mt7622-tphy + - mediatek,mt8163-tphy - mediatek,mt8516-tphy - const: mediatek,generic-tphy-v1 - items: From 856593cdc128ba8473615927313fe4f714d46924 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 13:06:50 +0100 Subject: [PATCH 027/126] dt-bindings: usb: Add binding for MT8163 MUSB Add a devicetree binding for MUSB on the MT8163 SoC. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/usb/mediatek,musb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml index a39d38db771471..654aa67e32e200 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml @@ -17,6 +17,7 @@ properties: compatible: items: - enum: + - mediatek,mt8163-musb - mediatek,mt8516-musb - mediatek,mt2701-musb - mediatek,mt7623-musb From 4fbab00f8766b76116778b34ab29ea3571b7444a Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Mon, 5 May 2025 01:06:46 +0100 Subject: [PATCH 028/126] phy: phy-mtk-tphy: Fix device and host mode for mobile SoCs AVALID reg is needed for device mode, and VBUSVALID for host mode Tested on MT6789 and MT6771. Signed-off-by: Arseniy Velikanov --- drivers/phy/mediatek/phy-mtk-tphy.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index acf5065295072c..855a559a2ee8e3 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -112,6 +112,10 @@ #define U3P_U2PHYDTM1 0x06C #define P2C_RG_UART_EN BIT(16) #define P2C_FORCE_IDDIG BIT(9) +#define P2C_FORCE_AVALID BIT(10) +#define P2C_FORCE_SESSEND BIT(12) +#define P2C_FORCE_VBUSVALID BIT(13) + #define P2C_RG_VBUSVALID BIT(5) #define P2C_RG_SESSEND BIT(4) #define P2C_RG_AVALID BIT(2) @@ -883,6 +887,9 @@ static void u2_phy_instance_power_on(struct mtk_tphy *tphy, mtk_phy_set_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); } + + mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_FORCE_AVALID | P2C_FORCE_VBUSVALID | P2C_FORCE_SESSEND); + dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); } From a19063b8efd6a8087a1c3931ac425c46dbd43a54 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 13:10:36 +0100 Subject: [PATCH 029/126] arm64: dts: mediatek: mt8163: Add T-PHY and USB Add device tree nodes for the USB T-PHY and MUSB controller on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 52 ++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 854f5bb2343aac..071345820f1bfe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include @@ -319,6 +320,43 @@ status = "disabled"; }; + usb0: usb@11200000 { + compatible = "mediatek,mt8163-musb", "mediatek,mtk-musb"; + reg = <0 0x11200000 0 0x1000>; + interrupts = ; + interrupt-names = "mc"; + phys = <&u2port0 PHY_TYPE_USB2>; + dr_mode = "otg"; + clocks = <&infracfg CLK_INFRA_USB>, + <&infracfg CLK_INFRA_USB_MCU>, + <&apmixedsys CLK_APMIXED_UNIVPLL>; + clock-names = "main", "mcu", "univpll"; + status = "disabled"; + }; + + u2phy0: t-phy@11210000 { + compatible = "mediatek,mt8163-tphy", "mediatek,generic-tphy-v1"; + reg = <0 0x11210000 0 0x0800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port0: usb-phy@11210800 { + reg = <0 0x11210800 0 0x0100>; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u2port1: usb-phy@11210900 { + reg = <0 0x11210900 0 0x0100>; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8163-mmc", "mediatek,mt2701-mmc"; reg = <0 0x11230000 0 0x1000>; @@ -349,5 +387,19 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + usb1: usb@11270000 { + compatible = "mediatek,mt8163-musb", "mediatek,mtk-musb"; + reg = <0 0x11270000 0 0x1000>; + interrupts = ; + interrupt-names = "mc"; + phys = <&u2port1 PHY_TYPE_USB2>; + dr_mode = "otg"; + clocks = <&infracfg CLK_INFRA_ICUSB>, + <&infracfg CLK_INFRA_USB_MCU>, + <&apmixedsys CLK_APMIXED_UNIVPLL>; + clock-names = "main", "mcu", "univpll"; + status = "disabled"; + }; }; }; From fa99baf12ec3cfa2bda77667415d33b3eb05ec8d Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 15:15:11 +0100 Subject: [PATCH 030/126] dt-bindings: i2c: i2c-mt65xx: Add binding for MT8163 I2C The I2C controller on the MT8163 SoC is functionally identical to that of the one on the MT8173 SoC, so reuse its binding. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index ecd5783f001b3e..281cb09fafc261 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -49,6 +49,7 @@ properties: - items: - enum: - mediatek,mt6795-i2c + - mediatek,mt8163-i2c - const: mediatek,mt8173-i2c - items: - enum: From 2a14c5a0a9fc8873254618e0cde39a8f01843792 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 15:16:01 +0100 Subject: [PATCH 031/126] arm64: dts: mediatek: mt8163: Add I2C Add device nodes for the three I2C controllers on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 071345820f1bfe..ac329164a4964b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -320,6 +320,42 @@ status = "disabled"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt8163-i2c", "mediatek,mt8173-i2c"; + reg = <0 0x11007000 0 0x70>, <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <10>; + clocks = <&infracfg CLK_INFRA_I2C0>, <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8163-i2c", "mediatek,mt8173-i2c"; + reg = <0 0x11008000 0 0x70>, <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <10>; + clocks = <&infracfg CLK_INFRA_I2C1>, <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8163-i2c", "mediatek,mt8173-i2c"; + reg = <0 0x11009000 0 0x70>, <0 0x11000280 0 0x80>; + interrupts = ; + clock-div = <10>; + clocks = <&infracfg CLK_INFRA_I2C2>, <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + usb0: usb@11200000 { compatible = "mediatek,mt8163-musb", "mediatek,mtk-musb"; reg = <0 0x11200000 0 0x1000>; From cbde53e8935cc67d9e9c1f394f2c84442d4329a3 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 17:28:25 +0100 Subject: [PATCH 032/126] dt-bindings: spi: Add binding for MT8163 SPI Add a device tree binding for the SPI controller on the MT8163 SoC, re-using the MT2712 driver and binding. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml index 3bf3eb1f872891..c8ea0322ab959e 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml @@ -22,6 +22,7 @@ properties: - const: mediatek,mt7622-spi - items: - enum: + - mediatek,mt8163-spi - mediatek,mt8516-spi - const: mediatek,mt2712-spi - items: From 7e602fc52cac6a82bf4cde7dd7240d819123d358 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 17:34:01 +0100 Subject: [PATCH 033/126] arm64: dts: mediatek: mt8163: Add SPI Add device tree node for the SPI controller on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index ac329164a4964b..af65c594283fb5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -356,6 +356,21 @@ status = "disabled"; }; + spi: spi@1100a000 { + compatible = "mediatek,mt8163-spi", "mediatek,mt2712-spi"; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + assigned-clocks = <&infracfg CLK_INFRA_SPI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SPI_SEL>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + usb0: usb@11200000 { compatible = "mediatek,mt8163-musb", "mediatek,mtk-musb"; reg = <0 0x11200000 0 0x1000>; From 6834b0d0bfbd710e13d28cfa60a4e434f010e26d Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 18:25:18 +0100 Subject: [PATCH 034/126] dt-bindings: iommu: Add bindings for MT8163 M4U Add device tree bindings for the M4U on MT8163. Signed-off-by: Ben Grisdale --- .../bindings/iommu/mediatek,iommu.yaml | 2 + include/dt-bindings/memory/mt8163-larb-port.h | 66 +++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 include/dt-bindings/memory/mt8163-larb-port.h diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 79c573c47b08ea..4f455696d0eab5 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -75,6 +75,7 @@ properties: - mediatek,mt6779-m4u # generation two - mediatek,mt6795-m4u # generation two - mediatek,mt6893-iommu-mm # generation two + - mediatek,mt8163-m4u # generation two - mediatek,mt8167-m4u # generation two - mediatek,mt8173-m4u # generation two - mediatek,mt8183-m4u # generation two @@ -137,6 +138,7 @@ properties: dt-binding/memory/mt6779-larb-port.h for mt6779, dt-binding/memory/mt6795-larb-port.h for mt6795, dt-binding/memory/mediatek,mt6893-memory-port.h for mt6893, + dt-binding/memory/mt8163-larb-port.h for mt8163, dt-binding/memory/mt8167-larb-port.h for mt8167, dt-binding/memory/mt8173-larb-port.h for mt8173, dt-binding/memory/mt8183-larb-port.h for mt8183, diff --git a/include/dt-bindings/memory/mt8163-larb-port.h b/include/dt-bindings/memory/mt8163-larb-port.h new file mode 100644 index 00000000000000..729da1f84d924c --- /dev/null +++ b/include/dt-bindings/memory/mt8163-larb-port.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ +#ifndef _DT_BINDINGS_MEMORY_MT8163_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8163_LARB_PORT_H_ + +#include + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_UFOD_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_UFOD_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 7) +#define M4U_PORT_UFOD_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 8) +#define M4U_PORT_UFOD_RDMA3 MTK_M4U_ID(M4U_LARB0_ID, 9) +#define M4U_PORT_UFOD_RDMA4 MTK_M4U_ID(M4U_LARB0_ID, 10) +#define M4U_PORT_UFOD_RDMA5 MTK_M4U_ID(M4U_LARB0_ID, 11) +#define M4U_PORT_UFOD_RDMA6 MTK_M4U_ID(M4U_LARB0_ID, 12) +#define M4U_PORT_UFOD_RDMA7 MTK_M4U_ID(M4U_LARB0_ID, 13) +#define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 14) +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 15) +#define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 16) + +/* larb1 */ +#define M4U_PORT_VDEC_MC MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_VDEC_PP MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_VDEC_VLD MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_VDEC_AVC_MV MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_VDEC_PRED_RD MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_VDEC_PRED_WR MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_VDEC_PPWRAP MTK_M4U_ID(M4U_LARB1_ID, 6) + +/* larb2 */ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 5) + +/* larb3 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) +#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 6) +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 7) +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 8) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 9) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 10) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 11) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 12) + +#endif /* _DT_BINDINGS_MEMORY_MT8163_LARB_PORT_H_ */ From 527c36c8b876e3c842e355509e39fecfaf565112 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 18:39:56 +0100 Subject: [PATCH 035/126] iommu: mtk_iommu: Add suport for MT8163 M4U Add support for the M4U on the MT8163 SoC. Signed-off-by: Ben Grisdale --- drivers/iommu/mtk_iommu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 2be990c108de2b..9ddf0b51d129d3 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -169,6 +169,7 @@ enum mtk_iommu_plat { M4U_MT2712, M4U_MT6779, M4U_MT6795, + M4U_MT8163, M4U_MT8167, M4U_MT8173, M4U_MT8183, @@ -1627,6 +1628,18 @@ static const struct mtk_iommu_plat_data mt6893_data = { {0, 14, 16}, {0, 13, 18, 17}}, }; +static const struct mtk_iommu_plat_data mt8163_data = { + .m4u_plat = M4U_MT8163, + .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | + TF_PORT_TO_ADDR_MT8173, + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, + .banks_num = 1, + .banks_enable = {true}, + .iova_region = single_domain, + .iova_region_nr = ARRAY_SIZE(single_domain), + .larbid_remap = {{0}, {1}, {2}, {3}}, /* Linear mapping. */ +}; + static const struct mtk_iommu_plat_data mt8167_data = { .m4u_plat = M4U_MT8167, .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, @@ -1904,6 +1917,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = { { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, { .compatible = "mediatek,mt6893-iommu-mm", .data = &mt6893_data}, + { .compatible = "mediatek,mt8163-m4u", .data = &mt8163_data}, { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, From 35a783743894c6c1b91fdb19eabbb9e34accc1d1 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 18:44:01 +0100 Subject: [PATCH 036/126] dt-bindings: memory: mtk-smi: Add bindings for MT8163 SMI Add device tree bindings for SMI on the MT8163 SoC. Signed-off-by: Ben Grisdale --- .../bindings/memory-controllers/mediatek,smi-common.yaml | 2 ++ .../bindings/memory-controllers/mediatek,smi-larb.yaml | 1 + 2 files changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index 0762e0ff66ef02..b2eb246ce90ca1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt6779-smi-common - mediatek,mt6795-smi-common - mediatek,mt6893-smi-common + - mediatek,mt8163-smi-common - mediatek,mt8167-smi-common - mediatek,mt8173-smi-common - mediatek,mt8183-smi-common @@ -156,6 +157,7 @@ allOf: - mediatek,mt2712-smi-common - mediatek,mt6795-smi-common - mediatek,mt8167-smi-common + - mediatek,mt8163-smi-common - mediatek,mt8173-smi-common then: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 2e7fac4b50945d..f3580f1b6e3fc0 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt6779-smi-larb - mediatek,mt6795-smi-larb - mediatek,mt6893-smi-larb + - mediatek,mt8163-smi-larb - mediatek,mt8167-smi-larb - mediatek,mt8173-smi-larb - mediatek,mt8183-smi-larb From 7357c33aab3d1440126de0f00457e487f9e43b81 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 18:49:01 +0100 Subject: [PATCH 037/126] memory: mtk-smi: Add support for MT8163 SMI Add support for SMI common and larbs on the MT8163 SoC. The M4U on this SoC has 4 LARBs and one common SMI instance without any sub common and gals. The smi-common configuration is specific to this SoC. But, on the LARB side, this is similar to that of MT8173, in the sense that it doesn't need the port in LARB, and the register layout is also compatible with that one, which allows us to re-use the smi-larb platform data struct from MT8173. Signed-off-by: Ben Grisdale --- drivers/memory/mtk-smi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index aaeba8ab211e97..7fbeab9aa861ff 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -551,6 +551,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173}, {.compatible = "mediatek,mt6893-smi-larb", .data = &mtk_smi_larb_mt6893}, + {.compatible = "mediatek,mt8163-smi-larb", .data = &mtk_smi_larb_mt8173}, {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, @@ -746,6 +747,12 @@ static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_ {SMI_READ_FIFO_TH, 0x191f}, }; +static const struct mtk_smi_reg_pair mtk_smi_common_mt8163_init[SMI_COMMON_INIT_REGS_NR] = { + {SMI_L1_ARB, 0x1b}, + {SMI_M4U_TH, 0xf7e19085}, + {SMI_READ_FIFO_TH, 0x1d1f}, +}; + static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { {SMI_L1LEN, 0xb}, {SMI_M4U_TH, 0xe100e10}, @@ -783,6 +790,11 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt6893 = { F_MMU1_LARB(5) | F_MMU1_LARB(7), }; +static const struct mtk_smi_common_plat mtk_smi_common_mt8163 = { + .type = MTK_SMI_GEN2, + .init = mtk_smi_common_mt8163_init, +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { .type = MTK_SMI_GEN2, .has_gals = true, @@ -846,6 +858,7 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795}, {.compatible = "mediatek,mt6893-smi-common", .data = &mtk_smi_common_mt6893}, + {.compatible = "mediatek,mt8163-smi-common", .data = &mtk_smi_common_mt8163}, {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, From 892d5f0c4731b0a207761e90fa43de49cb13c71c Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 19:17:42 +0100 Subject: [PATCH 038/126] dt-bindings: power-controller: Add bindings for MT8163 SCPSYS Add device tree bindings for the power controller on the MT8163 SoC. Signed-off-by: Ben Grisdale --- .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 1 + .../bindings/power/mediatek,power-controller.yaml | 2 ++ .../power/mediatek,mt8163-power-controller.h | 15 +++++++++++++++ 3 files changed, 18 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt8163-power-controller.h diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml index 4cafa381979bf3..8d04ebcf5f829c 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml @@ -21,6 +21,7 @@ properties: - enum: - mediatek,mt6795-scpsys - mediatek,mt6893-scpsys + - mediatek,mt8163-scpsys - mediatek,mt8167-scpsys - mediatek,mt8173-scpsys - mediatek,mt8183-scpsys diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 07f046277f8a6a..de232e81e341a3 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt6735-power-controller - mediatek,mt6795-power-controller - mediatek,mt6893-power-controller + - mediatek,mt8163-power-controller - mediatek,mt8167-power-controller - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller @@ -103,6 +104,7 @@ $defs: Power domain index. Valid values are defined in: "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain. + "include/dt-bindings/power/mediatek,mt8163-power-controller.h" - for MT8163 type power domain. "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. diff --git a/include/dt-bindings/power/mediatek,mt8163-power-controller.h b/include/dt-bindings/power/mediatek,mt8163-power-controller.h new file mode 100644 index 00000000000000..b0cc0430c1ed84 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8163-power-controller.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_MT8163_POWER_CONTROLLER_H +#define _DT_BINDINGS_POWER_MT8163_POWER_CONTROLLER_H + +#define MT8163_POWER_DOMAIN_MM 0 +#define MT8163_POWER_DOMAIN_VDEC 1 +#define MT8163_POWER_DOMAIN_VENC 2 +#define MT8163_POWER_DOMAIN_ISP 3 +#define MT8163_POWER_DOMAIN_CONN 4 +#define MT8163_POWER_DOMAIN_AUDIO 5 +#define MT8163_POWER_DOMAIN_MFG_ASYNC 6 +#define MT8163_POWER_DOMAIN_MFG 7 + +#endif /* _DT_BINDINGS_POWER_MT8163_POWER_CONTROLLER_H */ From f439d5bcbf15ff4b54b11f40d0d1d14c252bfcfe Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 19:18:30 +0100 Subject: [PATCH 039/126] pmdomain: mtk-pm-domains: Add support for MT8163 Add power domain definitions for the MT8163 SoC. Signed-off-by: Ben Grisdale --- drivers/pmdomain/mediatek/mt8163-pm-domains.h | 108 ++++++++++++++++++ drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 + include/linux/soc/mediatek/infracfg.h | 17 +++ 3 files changed, 130 insertions(+) create mode 100644 drivers/pmdomain/mediatek/mt8163-pm-domains.h diff --git a/drivers/pmdomain/mediatek/mt8163-pm-domains.h b/drivers/pmdomain/mediatek/mt8163-pm-domains.h new file mode 100644 index 00000000000000..596ea556d12b0d --- /dev/null +++ b/drivers/pmdomain/mediatek/mt8163-pm-domains.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#ifndef __SOC_MEDIATEK_MT8163_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8163_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8163 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8163[] = { + [MT8163_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = PWR_STATUS_VDEC, + .ctl_offs = SPM_VDE_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8163_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = SPM_VEN_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT8163_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = SPM_ISP_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + }, + [MT8163_POWER_DOMAIN_MM] = { + .name = "mm", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = SPM_DIS_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8163_TOP_AXI_PROT_EN_MM_M0), + }, + }, + [MT8163_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = SPM_AUDIO_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT8163_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = PWR_STATUS_MFG_ASYNC, + .ctl_offs = SPM_MFG_ASYNC_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = 0, + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8163_TOP_AXI_PROT_EN_MFG_M0 | + MT8163_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), + }, + }, + [MT8163_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = SPM_MFG_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(13, 8), + .sram_pdn_ack_bits = GENMASK(16, 16), + }, + [MT8163_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = SPM_CONN_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = 0, + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8163_TOP_AXI_PROT_EN_CCI_M2 | + MT8163_TOP_AXI_PROT_EN_CONN2EMI | + MT8163_TOP_AXI_PROT_EN_CONN2PERI), + }, + }, +}; + +static const struct scpsys_soc_data mt8163_scpsys_data = { + .domains_data = scpsys_domain_data_mt8163, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8163), +}; + +#endif /* __SOC_MEDIATEK_MT8163_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index e1cfd42234734f..3a87b16107365c 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -21,6 +21,7 @@ #include "mt6735-pm-domains.h" #include "mt6795-pm-domains.h" #include "mt6893-pm-domains.h" +#include "mt8163-pm-domains.h" #include "mt8167-pm-domains.h" #include "mt8173-pm-domains.h" #include "mt8183-pm-domains.h" @@ -1156,6 +1157,10 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt6893-power-controller", .data = &mt6893_scpsys_data, }, + { + .compatible = "mediatek,mt8163-power-controller", + .data = &mt8163_scpsys_data, + }, { .compatible = "mediatek,mt8167-power-controller", .data = &mt8167_scpsys_data, diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 9956e18c5ffa93..13f863b8b0c0e0 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -396,6 +396,23 @@ #define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6)) #define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7) +#define MT8163_TOP_AXI_PROT_EN_CCI_M1 BIT(0) +#define MT8163_TOP_AXI_PROT_EN_MM_M0 BIT(1) +#define MT8163_TOP_AXI_PROT_EN_MMAPB_S BIT(6) +#define MT8163_TOP_AXI_PROT_EN_L2C_M2 BIT(9) +#define MT8163_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) +#define MT8163_TOP_AXI_PROT_EN_L2SS_AFF BIT(12) +#define MT8163_TOP_AXI_PROT_EN_CCI_M2 BIT(13) +#define MT8163_TOP_AXI_PROT_EN_CONN2EMI BIT(14) +#define MT8163_TOP_AXI_PROT_EN_CONN2PERI BIT(15) +#define MT8163_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) +#define MT8163_TOP_AXI_PROT_EN_CQ_DMA BIT(18) +#define MT8163_TOP_AXI_PROT_EN_GCPU BIT(19) +#define MT8163_TOP_AXI_PROT_EN_IOMMU BIT(20) +#define MT8163_TOP_AXI_PROT_EN_MFG_M0 BIT(21) +#define MT8163_TOP_AXI_PROT_EN_MFG_M1 BIT(22) +#define MT8163_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) + #define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) #define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) #define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) From f48f850c9ad824ea44bfeddec05a4ad697a66a9b Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 19:36:21 +0100 Subject: [PATCH 040/126] arm64: dts: mediatek: mt8163: Add SPM Add device tree nodes for the System Power Manager (SPM) on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 69 ++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index af65c594283fb5..19a41d916c95e0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -151,6 +152,74 @@ reg = <0 0x10005000 0 0x1000>; }; + scpsys: syscon@10006000 { + compatible = "mediatek,mt8163-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + spm: power-controller { + compatible = "mediatek,mt8163-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* Power domains of the SoC */ + power-domain@MT8163_POWER_DOMAIN_MM { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8163_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + + power-domain@MT8163_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + + power-domain@MT8163_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + + power-domain@MT8163_POWER_DOMAIN_CONN { + reg = ; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8163_POWER_DOMAIN_AUDIO { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8163_POWER_DOMAIN_MFG_ASYNC { + reg = ; + clocks = <&topckgen CLK_TOP_MFG_SEL>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + mediatek,infracfg = <&infracfg>; + + power-domain@MT8163_POWER_DOMAIN_MFG { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8163-wdt"; reg = <0 0x10007000 0 0x1000>; From e239d9a7482968722f613d56eef47b16f064c6e1 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 20:01:38 +0100 Subject: [PATCH 041/126] dt-bindings: gpu: arm-mali-midgard: Add binding for MT8163 GPU Add a device tree binding for the ARM Mali-T720 GPU on the MT8163 SoC. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index a7192622e12054..224fc7b06b7b08 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: - allwinner,sun50i-h6-mali + - mediatek,mt8163-mali - const: arm,mali-t720 - items: - enum: From 5439e10bc41354c2e65d86be90c10ac05e06871d Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 20:38:28 +0100 Subject: [PATCH 042/126] dt-bindings: clock: Add bindings for MT8163 syscon clocks Add device tree bindings for MT8163 syscon clocks. Signed-off-by: Ben Grisdale --- .../bindings/clock/mediatek,syscon.yaml | 5 ++++ .../clock/mediatek,mt8163-audsys.h | 26 +++++++++++++++++++ .../clock/mediatek,mt8163-imgsys.h | 14 ++++++++++ .../clock/mediatek,mt8163-mfgcfg.h | 8 ++++++ .../clock/mediatek,mt8163-vdecsys.h | 9 +++++++ .../clock/mediatek,mt8163-vencsys.h | 11 ++++++++ 6 files changed, 73 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt8163-audsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt8163-imgsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt8163-mfgcfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt8163-vdecsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt8163-vencsys.h diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml index a52f90bfc9f92b..e5fef4c8b0620f 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml @@ -45,6 +45,11 @@ properties: - mediatek,mt6797-imgsys - mediatek,mt6797-vdecsys - mediatek,mt6797-vencsys + - mediatek,mt8163-audsys + - mediatek,mt8163-imgsys + - mediatek,mt8163-mfgcfg + - mediatek,mt8163-vdecsys + - mediatek,mt8163-vencsys - mediatek,mt8167-imgsys - mediatek,mt8167-mfgcfg - mediatek,mt8167-vdecsys diff --git a/include/dt-bindings/clock/mediatek,mt8163-audsys.h b/include/dt-bindings/clock/mediatek,mt8163-audsys.h new file mode 100644 index 00000000000000..77a6ac515d5601 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8163-audsys.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_MT8163_AUDSYS_H +#define _DT_BINDINGS_CLOCK_MT8163_AUDSYS_H + +#define CLK_AUDIO_AFE 0 +#define CLK_AUDIO_I2S 1 +#define CLK_AUDIO_22M 2 +#define CLK_AUDIO_24M 3 +#define CLK_AUDIO_SPDF2 4 +#define CLK_AUDIO_APLL2_TUNER 5 +#define CLK_AUDIO_APLL_TUNER 6 +#define CLK_AUDIO_HDMI 7 +#define CLK_AUDIO_SPDF 8 +#define CLK_AUDIO_ADC 9 +#define CLK_AUDIO_DAC 10 +#define CLK_AUDIO_DAC_PREDIS 11 +#define CLK_AUDIO_TML 12 +#define CLK_AUDIO_APLL1_DIV0 13 +#define CLK_AUDIO_APLL2_DIV0 14 +#define CLK_AUDIO_APLL_I2S0 15 +#define CLK_AUDIO_APLL_I2S1 16 +#define CLK_AUDIO_APLL_I2S2 17 +#define CLK_AUDIO_APLL_I2S3 18 + +#endif /* _DT_BINDINGS_CLOCK_MT8163_AUDSYS_H */ diff --git a/include/dt-bindings/clock/mediatek,mt8163-imgsys.h b/include/dt-bindings/clock/mediatek,mt8163-imgsys.h new file mode 100644 index 00000000000000..1b683c9882d65f --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8163-imgsys.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_MT8163_IMGSYS_H +#define _DT_BINDINGS_CLOCK_MT8163_IMGSYS_H + +#define CLK_IMG_LARB2_SMI 0 +#define CLK_IMG_JPGENC 1 +#define CLK_IMG_CAM_SMI 2 +#define CLK_IMG_CAM_CAM 3 +#define CLK_IMG_SEN_TG 4 +#define CLK_IMG_SEN_CAM 5 +#define CLK_IMG_CAM_SV 6 + +#endif /* _DT_BINDINGS_CLOCK_MT8163_IMGSYS_H */ diff --git a/include/dt-bindings/clock/mediatek,mt8163-mfgcfg.h b/include/dt-bindings/clock/mediatek,mt8163-mfgcfg.h new file mode 100644 index 00000000000000..52524994f9ff1b --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8163-mfgcfg.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_MT8163_MFGCFG_H +#define _DT_BINDINGS_CLOCK_MT8163_MFGCFG_H + +#define CLK_MFG_BG3D 0 + +#endif /* _DT_BINDINGS_CLOCK_MT8163_MFGCFG_H */ diff --git a/include/dt-bindings/clock/mediatek,mt8163-vdecsys.h b/include/dt-bindings/clock/mediatek,mt8163-vdecsys.h new file mode 100644 index 00000000000000..6bb9faa1864c3f --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8163-vdecsys.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_MT8163_VDECSYS_H +#define _DT_BINDINGS_CLOCK_MT8163_VDECSYS_H + +#define CLK_VDEC_CKEN 0 +#define CLK_VDEC_LARB_CKEN 1 + +#endif /* _DT_BINDINGS_CLOCK_MT8163_VDECSYS_H */ diff --git a/include/dt-bindings/clock/mediatek,mt8163-vencsys.h b/include/dt-bindings/clock/mediatek,mt8163-vencsys.h new file mode 100644 index 00000000000000..5cea90c8fbfafc --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8163-vencsys.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_MT8163_VENCSYS_H +#define _DT_BINDINGS_CLOCK_MT8163_VENCSYS_H + +#define CLK_VENC_CKE0 0 +#define CLK_VENC_CKE1 1 +#define CLK_VENC_CKE2 2 +#define CLK_VENC_CKE3 3 + +#endif /* _DT_BINDINGS_CLOCK_MT8163_VENCSYS_H */ From d8754c8f41b4ab99b87f0f61391bbdc87799d733 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 20:39:14 +0100 Subject: [PATCH 043/126] clk: mediatek: Add support for MT8163 syscon clocks Add drivers to provide support for syscon clocks on MT8163 SoC. Signed-off-by: Ben Grisdale --- drivers/clk/mediatek/Kconfig | 35 +++++++ drivers/clk/mediatek/Makefile | 5 + drivers/clk/mediatek/clk-mt8163-audsys.c | 113 ++++++++++++++++++++++ drivers/clk/mediatek/clk-mt8163-imgsys.c | 56 +++++++++++ drivers/clk/mediatek/clk-mt8163-mfgcfg.c | 50 ++++++++++ drivers/clk/mediatek/clk-mt8163-vdecsys.c | 60 ++++++++++++ drivers/clk/mediatek/clk-mt8163-vencsys.c | 53 ++++++++++ 7 files changed, 372 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8163-audsys.c create mode 100644 drivers/clk/mediatek/clk-mt8163-imgsys.c create mode 100644 drivers/clk/mediatek/clk-mt8163-mfgcfg.c create mode 100644 drivers/clk/mediatek/clk-mt8163-vdecsys.c create mode 100644 drivers/clk/mediatek/clk-mt8163-vencsys.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index bf2ef045ae246c..b5e25124c67fd7 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -485,6 +485,41 @@ config COMMON_CLK_MT8163 help This driver supports MediaTek MT8163 basic clocks. +config COMMON_CLK_MT8163_AUDSYS + tristate "Clock driver for MediaTek MT8163 audiosys" + depends on COMMON_CLK_MT8163 + default COMMON_CLK_MT8163 + help + This driver supports MediaTek MT8163 audiosys clocks. + +config COMMON_CLK_MT8163_IMGSYS + tristate "Clock driver for MediaTek MT8163 imgsys" + depends on COMMON_CLK_MT8163 + default COMMON_CLK_MT8163 + help + This driver supports MediaTek MT8163 imgsys clocks. + +config COMMON_CLK_MT8163_MFGCFG + tristate "Clock driver for MediaTek MT8163 mfgcfg" + depends on COMMON_CLK_MT8163 + default COMMON_CLK_MT8163 + help + This driver supports MediaTek MT8163 mfgcfg clocks. + +config COMMON_CLK_MT8163_VDECSYS + tristate "Clock driver for MediaTek MT8163 vdecsys" + depends on COMMON_CLK_MT8163 + default COMMON_CLK_MT8163 + help + This driver supports MediaTek MT8163 vdecsys clocks. + +config COMMON_CLK_MT8163_VENCSYS + tristate "Clock driver for MediaTek MT8163 vencsys" + depends on COMMON_CLK_MT8163 + default COMMON_CLK_MT8163 + help + This driver supports MediaTek MT8163 vencsys clocks. + config COMMON_CLK_MT8167 tristate "Clock driver for MediaTek MT8167" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index b7c2896d3a8ee7..161673c662d1e6 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -74,6 +74,11 @@ obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135-apmixedsys.o clk-mt8135.o obj-$(CONFIG_COMMON_CLK_MT8163) += clk-mt8163-apmixedsys.o clk-mt8163-infracfg.o clk-mt8163-topckgen.o +obj-$(CONFIG_COMMON_CLK_MT8163_AUDSYS) += clk-mt8163-audsys.o +obj-$(CONFIG_COMMON_CLK_MT8163_IMGSYS) += clk-mt8163-imgsys.o +obj-$(CONFIG_COMMON_CLK_MT8163_MFGCFG) += clk-mt8163-mfgcfg.o +obj-$(CONFIG_COMMON_CLK_MT8163_VDECSYS) += clk-mt8163-vdecsys.o +obj-$(CONFIG_COMMON_CLK_MT8163_VENCSYS) += clk-mt8163-vencsys.o obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167-apmixedsys.o clk-mt8167.o obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o obj-$(CONFIG_COMMON_CLK_MT8167_IMGSYS) += clk-mt8167-img.o diff --git a/drivers/clk/mediatek/clk-mt8163-audsys.c b/drivers/clk/mediatek/clk-mt8163-audsys.c new file mode 100644 index 00000000000000..a153da3c2da7bc --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8163-audsys.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define AUDIO_CLK_AUDDIV_0 0x05a0 +#define AUDIO_CLK_AUDDIV_1 0x05a4 + +static const char * const apll_div_parents[] = { + "aud_1_sel", + "aud_2_sel" +}; + +static const struct mtk_gate_regs aud_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +#define GATE_AUD(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) + +static const struct mtk_gate aud_clks[] = { + GATE_AUD(CLK_AUDIO_AFE, "aud_afe", "audio_sel", 2), + GATE_AUD(CLK_AUDIO_I2S, "aud_i2s", NULL, 6), + GATE_AUD(CLK_AUDIO_22M, "aud_22m", "audio_sel", 8), + GATE_AUD(CLK_AUDIO_24M, "aud_24m", "audio_sel", 9), + GATE_AUD(CLK_AUDIO_SPDF2, "aud_spdf2", NULL, 11), + GATE_AUD(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tnr", "aud_2_sel", 18), + GATE_AUD(CLK_AUDIO_APLL_TUNER, "aud_apll_tnr", "aud_1_sel", 19), + GATE_AUD(CLK_AUDIO_HDMI, "aud_hdmi", NULL, 20), + GATE_AUD(CLK_AUDIO_SPDF, "aud_spdf", NULL, 21), + GATE_AUD(CLK_AUDIO_ADC, "aud_adc", "audio_sel", 24), + GATE_AUD(CLK_AUDIO_DAC, "aud_dac", "audio_sel", 25), + GATE_AUD(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel", 26), + GATE_AUD(CLK_AUDIO_TML, "aud_tml", "audio_sel", 27), +}; + +#define AUD_DIV_GATE(_id, _name, _parent, _div_shift, _gate_shift) \ + DIV_GATE(_id, _name, _parent, AUDIO_CLK_AUDDIV_0, _gate_shift, \ + AUDIO_CLK_AUDDIV_0, 3 /* div_width */, _div_shift) + +#define AUD_MUX_DIV(_id, _name, _mux_shift, _div_shift, _gate_shift) \ + MUX_DIV_GATE_FLAGS(_id, _name, apll_div_parents, AUDIO_CLK_AUDDIV_0, \ + _mux_shift, 1 /* mux_width */, AUDIO_CLK_AUDDIV_1, \ + _div_shift, 8 /* div_width */, AUDIO_CLK_AUDDIV_0, \ + _gate_shift, 0) + +static const struct mtk_composite aud_divs[] = { + AUD_DIV_GATE(CLK_AUDIO_APLL1_DIV0, "aud_apll1_div0", "aud_1_sel", 24, 0), + AUD_DIV_GATE(CLK_AUDIO_APLL2_DIV0, "aud_apll2_div0", "aud_2_sel", 28, 1), + AUD_MUX_DIV(CLK_AUDIO_APLL_I2S0, "aud_apll_i2s0", 8, 0, 2), + AUD_MUX_DIV(CLK_AUDIO_APLL_I2S1, "aud_apll_i2s1", 9, 8, 3), + AUD_MUX_DIV(CLK_AUDIO_APLL_I2S2, "aud_apll_i2s2", 10, 16, 4), + AUD_MUX_DIV(CLK_AUDIO_APLL_I2S3, "aud_apll_i2s3", 11, 24, 5), +}; + +static const struct mtk_clk_desc aud_desc = { + .clks = aud_clks, + .num_clks = ARRAY_SIZE(aud_clks), + .composite_clks = aud_divs, + .num_composite_clks = ARRAY_SIZE(aud_divs), +}; + +static int clk_mt8163_audio_probe(struct platform_device *pdev) +{ + int ret; + + ret = mtk_clk_simple_probe(pdev); + if (ret) + return ret; + + ret = devm_of_platform_populate(&pdev->dev); + if (ret) + mtk_clk_simple_remove(pdev); + + return ret; +} + +static void clk_mt8163_audio_remove(struct platform_device *pdev) +{ + of_platform_depopulate(&pdev->dev); + mtk_clk_simple_remove(pdev); +} + +static const struct of_device_id of_match_clk_mt8163_audsys[] = { + { .compatible = "mediatek,mt8163-audsys", .data = &aud_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8163_audsys); + +static struct platform_driver clk_mt8163_audsys_drv = { + .probe = clk_mt8163_audio_probe, + .remove = clk_mt8163_audio_remove, + .driver = { + .name = "clk-mt8163-audsys", + .of_match_table = of_match_clk_mt8163_audsys, + }, +}; +module_platform_driver(clk_mt8163_audsys_drv); + +MODULE_AUTHOR("Ben Grisdale "); +MODULE_DESCRIPTION("MediaTek MT8163 audiosys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8163-imgsys.c b/drivers/clk/mediatek/clk-mt8163-imgsys.c new file mode 100644 index 00000000000000..08182def4bdf49 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8163-imgsys.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +static const struct mtk_gate_regs img_cg_regs = { + .set_ofs = 0x0004, + .clr_ofs = 0x0008, + .sta_ofs = 0x0000, +}; + +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate img_clks[] = { + GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0), + GATE_IMG(CLK_IMG_JPGENC, "img_jpgenc", "mm_sel", 4), + GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5), + GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6), + GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7), + GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8), + GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9), +}; + +static const struct mtk_clk_desc img_desc = { + .clks = img_clks, + .num_clks = ARRAY_SIZE(img_clks), +}; + +static const struct of_device_id of_match_clk_mt8163_imgsys[] = { + { .compatible = "mediatek,mt8163-imgsys", .data = &img_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8163_imgsys); + +static struct platform_driver clk_mt8163_imgsys_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8163-imgsys", + .of_match_table = of_match_clk_mt8163_imgsys, + }, +}; +module_platform_driver(clk_mt8163_imgsys_drv); + +MODULE_AUTHOR("Ben Grisdale "); +MODULE_DESCRIPTION("MediaTek MT8163 imgsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8163-mfgcfg.c b/drivers/clk/mediatek/clk-mt8163-mfgcfg.c new file mode 100644 index 00000000000000..4d9538ee598878 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8163-mfgcfg.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +static const struct mtk_gate_regs mfgcfg_cg_regs = { + .set_ofs = 0x0004, + .clr_ofs = 0x0008, + .sta_ofs = 0x0000, +}; + +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mfgcfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate mfgcfg_gates[] = { + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0), +}; + +static const struct mtk_clk_desc mfgcfg_clks = { + .clks = mfgcfg_gates, + .num_clks = ARRAY_SIZE(mfgcfg_gates), +}; + +static const struct of_device_id of_match_mt8163_mfgcfg[] = { + { .compatible = "mediatek,mt8163-mfgcfg", .data = &mfgcfg_clks }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_mt8163_mfgcfg); + +static struct platform_driver clk_mt8163_mfgcfg = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8163-mfgcfg", + .of_match_table = of_match_mt8163_mfgcfg, + }, +}; +module_platform_driver(clk_mt8163_mfgcfg); + +MODULE_AUTHOR("Ben Grisdale "); +MODULE_DESCRIPTION("Mediatek MT8163 mfgcfg clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8163-vdecsys.c b/drivers/clk/mediatek/clk-mt8163-vdecsys.c new file mode 100644 index 00000000000000..40f6a34b882043 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8163-vdecsys.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs vdec0_cg_regs = { + .set_ofs = 0x0000, + .clr_ofs = 0x0004, + .sta_ofs = 0x0000, +}; + +static const struct mtk_gate_regs vdec1_cg_regs = { + .set_ofs = 0x0008, + .clr_ofs = 0x000c, + .sta_ofs = 0x0008, +}; + +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate vdec_clks[] = { + GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0), + GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0), +}; + +static const struct mtk_clk_desc vdec_desc = { + .clks = vdec_clks, + .num_clks = ARRAY_SIZE(vdec_clks), +}; + +static const struct of_device_id of_match_clk_mt8163_vdecsys[] = { + { .compatible = "mediatek,mt8163-vdecsys", .data = &vdec_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8163_vdecsys); + +static struct platform_driver clk_mt8163_vdecsys_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8163-vdecsys", + .of_match_table = of_match_clk_mt8163_vdecsys, + }, +}; +module_platform_driver(clk_mt8163_vdecsys_drv); + +MODULE_AUTHOR("Ben Grisdale "); +MODULE_DESCRIPTION("MediaTek MT8163 vdecsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8163-vencsys.c b/drivers/clk/mediatek/clk-mt8163-vencsys.c new file mode 100644 index 00000000000000..3484b37daaebeb --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8163-vencsys.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs venc_cg_regs = { + .set_ofs = 0x0004, + .clr_ofs = 0x0008, + .sta_ofs = 0x0000, +}; + +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate venc_clks[] = { + GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0), + GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "mm_sel", 4), + GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "mm_sel", 8), + GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "mm_sel", 12), +}; + +static const struct mtk_clk_desc venc_desc = { + .clks = venc_clks, + .num_clks = ARRAY_SIZE(venc_clks), +}; + +static const struct of_device_id of_match_clk_mt8163_vencsys[] = { + { .compatible = "mediatek,mt8163-vencsys", .data = &venc_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8163_vencsys); + +static struct platform_driver clk_mt8163_vencsys_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8163-vencsys", + .of_match_table = of_match_clk_mt8163_vencsys, + }, +}; +module_platform_driver(clk_mt8163_vencsys_drv); + +MODULE_AUTHOR("Ben Grisdale "); +MODULE_DESCRIPTION("MediaTek MT8163 vencsys clocks driver"); +MODULE_LICENSE("GPL"); From 200bf838ea0f6eee385c134bd2745bc1b62ed149 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 21:03:42 +0100 Subject: [PATCH 044/126] arm64: dts: mediatek: mt8163: Add syscon clocks Add syscon clock controllers to the MT8163 device tree. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 19a41d916c95e0..446df08c6f1e6a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -6,9 +6,14 @@ #include #include +#include #include +#include #include +#include #include +#include +#include #include #include #include @@ -477,6 +482,12 @@ }; }; + audiosys: clock-controller@11220000 { + compatible = "mediatek,mt8163-audsys", "syscon"; + reg = <0 0x11220000 0 0x1000>; + #clock-cells = <1>; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8163-mmc", "mediatek,mt2701-mmc"; reg = <0 0x11230000 0 0x1000>; @@ -521,5 +532,29 @@ clock-names = "main", "mcu", "univpll"; status = "disabled"; }; + + mfgcfg: clock-controller@13000000 { + compatible = "mediatek,mt8163-mfgcfg", "syscon"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15000000 { + compatible = "mediatek,mt8163-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt8163-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt8163-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; }; }; From 03cbba5c21eff760ab92221e3ab3d1c7cef640f1 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 21:08:02 +0100 Subject: [PATCH 045/126] arm64: dts: mediatek: mt8163: Add Mali-T720 GPU Add device tree node for the Mali-T720 GPU used on the MT8163 SoC. GPU power on this platform appears to be provided by a fixed regulator at 1.5v; assumed from the fact that all operating points from the downstream gpufreq driver run at the same volt and the fact that the voltage scaling code is commented out [1]. [1]: https://github.com/amazon-oss/android_kernel_amazon_mt8163/blob/lineage-18.1/drivers/misc/mediatek/base/power/mt8163/mtk_gpufreq.c Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 446df08c6f1e6a..8afc6592dfdf0f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -25,6 +25,15 @@ interrupt-parent = <&sysirq>; compatible = "mediatek,mt8163"; + vgpu_1v15: regulator-vgpu { + compatible = "regulator-fixed"; + regulator-name = "vgpu-1v15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -539,6 +548,22 @@ #clock-cells = <1>; }; + gpu: gpu@13040000 { + compatible = "mediatek,mt8163-mali", "arm,mali-t720"; + reg = <0 0x13040000 0 0x4000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&mfgcfg CLK_MFG_BG3D>; + assigned-clocks = <&topckgen CLK_TOP_MFG_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_MMPLL>; + power-domains = <&spm MT8163_POWER_DOMAIN_MFG>; + mali-supply = <&vgpu_1v15>; + #cooling-cells = <2>; + status = "disabled"; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8163-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; From 828c968a1b7e5e52a8b98f8117b4412126758f4b Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 14 Feb 2026 01:19:16 +0000 Subject: [PATCH 046/126] arm64: dts: mediatek: mt8163: Add operating points for Mali GPU Define the operating points table for the Mali GPU on the MT8163 SoC. This SoC does not need complex voltage or clock scaling and instead just sets the rate of MMPLL to the desired frequency. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 8afc6592dfdf0f..35c220bc0f8434 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -25,6 +25,26 @@ interrupt-parent = <&sysirq>; compatible = "mediatek,mt8163"; + gpu_opp: opp-table-gpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + opp-microvolt = <1150000>; + }; + + opp-416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <1150000>; + }; + + opp-299000000 { + opp-hz = /bits/ 64 <299000000>; + opp-microvolt = <1150000>; + }; + }; + vgpu_1v15: regulator-vgpu { compatible = "regulator-fixed"; regulator-name = "vgpu-1v15"; @@ -560,6 +580,7 @@ assigned-clock-parents = <&apmixedsys CLK_APMIXED_MMPLL>; power-domains = <&spm MT8163_POWER_DOMAIN_MFG>; mali-supply = <&vgpu_1v15>; + operating-points-v2 = <&gpu_opp>; #cooling-cells = <2>; status = "disabled"; }; From b81f5433b44eb50aead4abe2aa1c482e675637a7 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 11:49:27 +0100 Subject: [PATCH 047/126] dt-bindings: regulator: fan53555: Add binding for Silergy SYM827 Add a devicetree binding for the Silergy SYM827 regulator. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml b/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml index 69bae90fc4b28f..70d7cf7d4da1a4 100644 --- a/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml +++ b/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml @@ -20,6 +20,7 @@ properties: - fcs,fan53526 - rockchip,rk8600 - rockchip,rk8602 + - silergy,sym827 - silergy,syr827 - silergy,syr828 - tcs,tcs4525 From 5da95a2316734912bec479cef8c43377f48cd438 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 31 Aug 2025 11:51:05 +0100 Subject: [PATCH 048/126] regulator: fan53555: Add support for Silergy SYM827 Add support for the Silergy SYM827 regulator in the fan53555 driver. Not much is known about this chip, apart from the fact that it appears to be another knock-off of the FAN53555 regulator. Voltage ranges are taken from the downstream driver. Signed-off-by: Ben Grisdale --- drivers/regulator/fan53555.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c index c282236959b180..1d98ee50896c90 100644 --- a/drivers/regulator/fan53555.c +++ b/drivers/regulator/fan53555.c @@ -116,10 +116,15 @@ enum { }; enum { + SILERGY_SYM82X = 1, SILERGY_SYR82X = 8, SILERGY_SYR83X = 9, }; +enum { + SILERGY_SYM827_CHIP_REV_12 = 12, +}; + struct fan53555_device_info { enum fan53555_vendor vendor; struct device *dev; @@ -393,6 +398,19 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) { /* Init voltage range and step */ switch (di->chip_id) { + case SILERGY_SYM82X: + switch (di->chip_rev) { + case SILERGY_SYM827_CHIP_REV_12: + di->vsel_min = 600000; + di->vsel_step = 12500; + break; + default: + dev_err(di->dev, + "Chip ID %d with rev %d not supported!\n", + di->chip_id, di->chip_rev); + return -EINVAL; + } + break; case SILERGY_SYR82X: case SILERGY_SYR83X: di->vsel_min = 712500; @@ -654,6 +672,9 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { }, { .compatible = "rockchip,rk8602", .data = (void *)RK8602_VENDOR_ROCKCHIP + }, { + .compatible = "silergy,sym827", + .data = (void *)FAN53555_VENDOR_SILERGY, }, { .compatible = "silergy,syr827", .data = (void *)FAN53555_VENDOR_SILERGY, @@ -761,6 +782,9 @@ static const struct i2c_device_id fan53555_id[] = { }, { .name = "rk8602", .driver_data = RK8602_VENDOR_ROCKCHIP + }, { + .name = "sym827", + .driver_data = FAN53555_VENDOR_SILERGY }, { .name = "syr827", .driver_data = FAN53555_VENDOR_SILERGY From 0d11c5e62cc9bc7e8df7947b41fd4effde0f7889 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 7 Sep 2025 13:59:24 +0100 Subject: [PATCH 049/126] cpufreq: mediatek-cpufreq: Add support for MT8163 Add support for cpufreq on the MT8163 platform. Signed-off-by: Ben Grisdale --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/mediatek-cpufreq.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index ff1204c666b197..fd3bb3235ba8e7 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -134,6 +134,7 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "mediatek,mt2712", }, { .compatible = "mediatek,mt7622", }, { .compatible = "mediatek,mt7623", }, + { .compatible = "mediatek,mt8163", }, { .compatible = "mediatek,mt8167", }, { .compatible = "mediatek,mt817x", }, { .compatible = "mediatek,mt8173", }, diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 052ca7cd2f4fd8..5bbd53790c0ab0 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -750,6 +750,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst __maybe_unus { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data }, + { .compatible = "mediatek,mt8163", .data = &mt7623_platform_data }, { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, From c3ba35537a8713566d1fc3ba967cd27df99214eb Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 7 Sep 2025 15:32:26 +0100 Subject: [PATCH 050/126] arm64: dts: mediatek: mt8163: Add CPU clocks and OPPs Add required CPU clocks and OPPs to enable cpufreq on MT8163. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 61 ++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 35c220bc0f8434..421507221532bd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -25,6 +25,51 @@ interrupt-parent = <&sysirq>; compatible = "mediatek,mt8163"; + cluster0_opp: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1150000>; + }; + + opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <1150000>; + }; + + opp-741000000 { + opp-hz = /bits/ 64 <741000000>; + opp-microvolt = <1150000>; + }; + + opp-871000000 { + opp-hz = /bits/ 64 <871000000>; + opp-microvolt = <1150000>; + }; + + opp-1050000000 { + opp-hz = /bits/ 64 <1050000000>; + opp-microvolt = <1150000>; + }; + + opp-1133000000 { + opp-hz = /bits/ 64 <1133000000>; + opp-microvolt = <1200000>; + }; + + opp-1216000000 { + opp-hz = /bits/ 64 <1216000000>; + opp-microvolt = <1250000>; + }; + + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1300000>; + }; + }; + gpu_opp: opp-table-gpu { compatible = "operating-points-v2"; opp-shared; @@ -63,6 +108,10 @@ compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&topckgen CLK_TOP_ARMPLL_DIVIDER_PLL1_EN>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; }; @@ -72,6 +121,10 @@ compatible = "arm,cortex-a53"; reg = <0x1>; enable-method = "psci"; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&topckgen CLK_TOP_ARMPLL_DIVIDER_PLL1_EN>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; }; @@ -81,6 +134,10 @@ compatible = "arm,cortex-a53"; reg = <0x2>; enable-method = "psci"; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&topckgen CLK_TOP_ARMPLL_DIVIDER_PLL1_EN>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; }; @@ -90,6 +147,10 @@ compatible = "arm,cortex-a53"; reg = <0x3>; enable-method = "psci"; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&topckgen CLK_TOP_ARMPLL_DIVIDER_PLL1_EN>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; }; From 66fb5d14a6fa2057bbdf428e808d77e984ce8f83 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 12 Dec 2025 13:39:35 +0000 Subject: [PATCH 051/126] arm64: dts: mediatek: mt8163: Add CPU cache information The MT8163 SoC's AP MCU subsystem has a Quad-core Cortex-A53 in a single cluster configuration, with the following cache configuration: - 32KB L1 I-cache: 2-way set associative - 32KB L1 D-cache: 4-way set associative There is also a 512KB unified L2 cache, shared amongst all CPUs in the cluster. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 421507221532bd..e0a0a7187efbd1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -114,6 +114,13 @@ operating-points-v2 = <&cluster0_opp>; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; }; cpu1: cpu@1 { @@ -127,6 +134,13 @@ operating-points-v2 = <&cluster0_opp>; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; }; cpu2: cpu@2 { @@ -140,6 +154,13 @@ operating-points-v2 = <&cluster0_opp>; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; }; cpu3: cpu@3 { @@ -153,6 +174,13 @@ operating-points-v2 = <&cluster0_opp>; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; }; cpu-map { @@ -174,6 +202,15 @@ }; }; }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + }; }; psci { From 627d1923b1fe5026301e8a6dee313d8a2984db89 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 13 Dec 2025 01:33:33 +0000 Subject: [PATCH 052/126] dt-bindings: iio: adc: Add compatible for MT8163 Add a compatible string for the auxadc on the MT8163 SoC, reusing the compatible data from MT8173. Signed-off-by: Ben Grisdale --- .../devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml index d9e825e5054fe5..31dc6322bcd45c 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml @@ -39,6 +39,7 @@ properties: - items: - enum: - mediatek,mt6893-auxadc + - mediatek,mt8163-auxadc - mediatek,mt8183-auxadc - mediatek,mt8186-auxadc - mediatek,mt8188-auxadc From 08b213dc8a333d3cc68018c710f8d3df77b43a97 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 13 Dec 2025 01:34:54 +0000 Subject: [PATCH 053/126] arm64: dts: mediatek: mt8163: Add AUXADC Add a device node for the AUXADC on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index e0a0a7187efbd1..0b211b7567574a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -453,6 +453,15 @@ }; }; + auxadc: auxadc@11001000 { + compatible = "mediatek,mt8163-auxadc", "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + apdma: dma-controller@11000300 { compatible = "mediatek,mt8163-uart-dma", "mediatek,mt6577-uart-dma"; reg = <0 0x11000300 0 0x80>, From 5872d0bcb38be4f9647706d4589123f391ebc4e3 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 13 Dec 2025 02:38:25 +0000 Subject: [PATCH 054/126] dt-bindings: nvmem: Add compatible for MT8163 efuse Add a compatible string for the efuse region on the MT8163 SoC. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index f9323b3ecfc83e..aeb5af1f43feea 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -49,6 +49,7 @@ properties: - mediatek,mt7981-efuse - mediatek,mt7986-efuse - mediatek,mt7988-efuse + - mediatek,mt8163-efuse - mediatek,mt8173-efuse - mediatek,mt8183-efuse - mediatek,mt8189-efuse From b0955dcd0687ee6c13d9e773bbdef43f8184469f Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 13 Dec 2025 02:24:28 +0000 Subject: [PATCH 055/126] dt-bindings: thermal: mediatek: Add binding for MT8163 thermal Add a compatible string for the auxadc based thermal controller on the MT8163 SoC. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/thermal/mediatek,thermal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/mediatek,thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,thermal.yaml index 7bd0955e6d045d..9173e7d95387ba 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek,thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/mediatek,thermal.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt2712-thermal - mediatek,mt7622-thermal - mediatek,mt7986-thermal + - mediatek,mt8163-thermal - mediatek,mt8173-thermal - mediatek,mt8183-thermal - mediatek,mt8365-thermal From d2d851570228b21981051b5074f119c35020fbc4 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 13 Dec 2025 02:25:10 +0000 Subject: [PATCH 056/126] thermal: mediatek: Add support for MT8163 auxadc thermal Add support for the auxadc based thermal controller on the MT8163 SoC. Signed-off-by: Ben Grisdale --- drivers/thermal/mediatek/auxadc_thermal.c | 82 +++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/thermal/mediatek/auxadc_thermal.c b/drivers/thermal/mediatek/auxadc_thermal.c index 9ee2e7283435ac..8f003c419ae272 100644 --- a/drivers/thermal/mediatek/auxadc_thermal.c +++ b/drivers/thermal/mediatek/auxadc_thermal.c @@ -296,6 +296,29 @@ enum mtk_thermal_version { #define MT8365_TS2 1 #define MT8365_TS3 2 +/* MT8163 thermal sensors */ +#define MT8163_TS1 0 +#define MT8163_TS2 1 +#define MT8163_TS3 2 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8163_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8163 */ +#define MT8163_NUM_SENSORS 3 + +/* The number of banks in the MT8163 */ +#define MT8163_NUM_ZONES 3 + +/* The number of sensing points per bank */ +#define MT8163_NUM_SENSORS_PER_ZONE 3 + +/* The number of controller in the MT8163 */ +#define MT8163_NUM_CONTROLLER 1 + +/* The calibration coefficient of sensor */ +#define MT8163_CALIBRATION 165 + struct mtk_thermal; struct thermal_bank_cfg { @@ -468,6 +491,28 @@ static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 }; static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 }; +/* MT8163 thermal sensor data */ +static const int mt8163_bank_data[MT8163_NUM_ZONES][3] = { + { MT8163_TS1, MT8163_TS2 }, + { MT8163_TS2 }, + { MT8163_TS1, MT8163_TS2, MT8163_TS3 }, +}; + +static const int mt8163_msr[MT8163_NUM_SENSORS_PER_ZONE] = { + TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 +}; + +static const int mt8163_adcpnp[MT8163_NUM_SENSORS_PER_ZONE] = { + TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 +}; + +static const int mt8163_mux_values[MT8163_NUM_SENSORS] = { 0, 1, 2 }; +static const int mt8163_tc_offset[MT8163_NUM_CONTROLLER] = { 0x0, }; + +static const int mt8163_vts_index[MT8163_NUM_SENSORS] = { + VTS1, VTS2, VTS3 +}; + /* * The MT8173 thermal controller has four banks. Each bank can read up to * four temperature sensors simultaneously. The MT8173 has a total of 5 @@ -695,6 +740,39 @@ static const struct mtk_thermal_data mt7986_thermal_data = { .apmixed_buffer_ctl_set = BIT(0), }; +/* + * The MT8163 thermal controller has three banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8163 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. + */ +static const struct mtk_thermal_data mt8163_thermal_data = { + .auxadc_channel = MT8163_TEMP_AUXADC_CHANNEL, + .num_banks = MT8163_NUM_ZONES, + .num_sensors = MT8163_NUM_SENSORS, + .vts_index = mt8163_vts_index, + .cali_val = MT8163_CALIBRATION, + .num_controller = MT8163_NUM_CONTROLLER, + .controller_offset = mt8163_tc_offset, + .need_switch_bank = true, + .bank_data = { + { + .num_sensors = 2, + .sensors = mt8163_bank_data[0], + }, { + .num_sensors = 1, + .sensors = mt8163_bank_data[1], + }, { + .num_sensors = 3, + .sensors = mt8163_bank_data[2], + }, + }, + .msr = mt8163_msr, + .adcpnp = mt8163_adcpnp, + .sensor_mux_values = mt8163_mux_values, + .version = MTK_THERMAL_V1, +}; + static bool mtk_thermal_temp_is_valid(int temp) { return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX); @@ -1133,6 +1211,10 @@ static int mtk_thermal_get_calibration_data(struct device *dev, } static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8163-thermal", + .data = (void *)&mt8163_thermal_data, + }, { .compatible = "mediatek,mt8173-thermal", .data = (void *)&mt8173_thermal_data, From 6eae318114ee44aa7016da7a0c7b41f8b664c3a6 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sat, 6 Dec 2025 22:15:51 +0000 Subject: [PATCH 057/126] thermal: mediatek: Create a new zone for each bank Currently, auxadc_thermal only creates a single thermal zone for all banks and reports the highest temperature reading from all of them. This isn't ideal especially if we want to have different throttling points for CPU / CCI / GPU. Refactor the driver to create a thermal zone for each bank. Signed-off-by: bengris32 --- drivers/thermal/mediatek/auxadc_thermal.c | 34 ++++++++++------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/drivers/thermal/mediatek/auxadc_thermal.c b/drivers/thermal/mediatek/auxadc_thermal.c index 8f003c419ae272..e337db1a8e0062 100644 --- a/drivers/thermal/mediatek/auxadc_thermal.c +++ b/drivers/thermal/mediatek/auxadc_thermal.c @@ -925,21 +925,13 @@ static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature) { - struct mtk_thermal *mt = thermal_zone_device_priv(tz); - int i; - int tempmax = INT_MIN; - - for (i = 0; i < mt->conf->num_banks; i++) { - struct mtk_thermal_bank *bank = &mt->banks[i]; + struct mtk_thermal_bank *bank = thermal_zone_device_priv(tz); - mtk_thermal_get_bank(bank); - - tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); + mtk_thermal_get_bank(bank); - mtk_thermal_put_bank(bank); - } + *temperature = mtk_thermal_bank_temperature(bank); - *temperature = tempmax; + mtk_thermal_put_bank(bank); return 0; } @@ -1367,14 +1359,18 @@ static int mtk_thermal_probe(struct platform_device *pdev) mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base, ctrl_id); - tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, - &mtk_thermal_ops); - if (IS_ERR(tzdev)) - return PTR_ERR(tzdev); + for (i = 0; i < mt->conf->num_banks; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + tzdev = devm_thermal_of_zone_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + if (IS_ERR(tzdev)) + return PTR_ERR(tzdev); - ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev); - if (ret) - dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); + ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev); + if (ret) + dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); + } return 0; } From 2dd52604acd84660cf1dd8dccd32ae50c0947aa7 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 13 Dec 2025 02:27:44 +0000 Subject: [PATCH 058/126] arm64: dts: mediatek: mt8163: Add thermal Add a device node for the auxadc based thermal controller on the MT8163 SoC and define thermal zones / trip points of the SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 121 +++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 0b211b7567574a..ca99c4d14fb7d9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -405,6 +405,17 @@ interrupt-controller; }; + efuse: efuse@10206000 { + compatible = "mediatek,mt8163-efuse", "mediatek,efuse"; + reg = <0 0x10206000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + thermal_calibration: calib@100 { + reg = <0x100 0xc>; + }; + }; + gic: interrupt-controller@10221000 { compatible = "arm,gic-400"; reg = <0 0x10221000 0 0x1000>, @@ -581,6 +592,20 @@ status = "disabled"; }; + thermal: thermal@1100b000 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt8163-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>, <&infracfg CLK_INFRA_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&infracfg MT8163_INFRA_RST0_THERM_CTRL>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + }; + usb0: usb@11200000 { compatible = "mediatek,mt8163-musb", "mediatek,mtk-musb"; reg = <0 0x11200000 0 0x1000>; @@ -710,4 +735,100 @@ #clock-cells = <1>; }; }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = <&thermal 0>; + sustainable-power = <1000>; + + trips { + threshold: trip-point0 { + temperature = <68000>; + hysteresis = <2000>; + type = "passive"; + }; + + target: trip-point1 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = <&thermal 1>; + sustainable-power = <1000>; + + trips { + gpu_alert: trip-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: trip-crit { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = <&gpu 1 THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&gpu_crit>; + cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; + }; + }; + }; + + soc_thermal: soc-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = <&thermal 2>; + sustainable-power = <1000>; + + trips { + soc_alert: trip-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit: trip-crit { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; }; From d86016245ca94ae3efb020fadd553e68d9e052ff Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 19 Dec 2025 16:19:35 +0000 Subject: [PATCH 059/126] dt-bindings: input: mediatek,mt6779-keypad: Add compatible for MT8163 Add a compatible for the matrix keypad controller on the MT8163 SoC. Signed-off-by: Ben Grisdale --- .../devicetree/bindings/input/mediatek,mt6779-keypad.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml index 914dd3283df330..6403e9de01379b 100644 --- a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - mediatek,mt6873-keypad + - mediatek,mt8163-keypad - mediatek,mt8183-keypad - mediatek,mt8365-keypad - mediatek,mt8516-keypad From 6458eb8394248b4d8889c3b849eada1c27fef681 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 19 Dec 2025 16:20:43 +0000 Subject: [PATCH 060/126] arm64: dts: mediatek: mt8163: Add matrix keypad controller Add a device tree node for the matrix keypad controller on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index ca99c4d14fb7d9..543c6a1c3b76d1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -397,6 +397,15 @@ clock-names = "spi", "wrap"; }; + keypad: keyboard@10010000 { + compatible = "mediatek,mt8163-keypad", "mediatek,mt6779-keypad"; + reg = <0 0x10010000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + sysirq: intpol-controller@10200620 { compatible = "mediatek,mt8163-sysirq", "mediatek,mt6577-sysirq"; reg = <0 0x10200620 0 0x20>; From 8d1249f3bf3b2b0d7f46b352e764b89dba73453b Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Wed, 28 Jan 2026 03:15:00 +0000 Subject: [PATCH 061/126] dt-bindings: rng: Add binding for MT8163 TRNG Add a compatible string for the TRNG (True Random Number Generator) hardware block on the MT8163 SoC, reusing the MT7623 compatible. Signed-off-by: Ben Grisdale --- Documentation/devicetree/bindings/rng/mtk-rng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.yaml b/Documentation/devicetree/bindings/rng/mtk-rng.yaml index 7e8dc62e5d3a62..ad91733de77b3e 100644 --- a/Documentation/devicetree/bindings/rng/mtk-rng.yaml +++ b/Documentation/devicetree/bindings/rng/mtk-rng.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt7622-rng - mediatek,mt7629-rng - mediatek,mt7986-rng + - mediatek,mt8163-rng - mediatek,mt8365-rng - mediatek,mt8516-rng - const: mediatek,mt7623-rng From 9eaedb36bcb7160e99cfa4dbe6f70db4b0216cb6 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Wed, 28 Jan 2026 03:17:16 +0000 Subject: [PATCH 062/126] arm64: dts: mediatek: mt8163: Add TRNG Add a device tree node for the TRNG (True Random Number Generator) block on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 543c6a1c3b76d1..4e4c2e1958a09c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -425,6 +425,13 @@ }; }; + rng@1020f000 { + compatible = "mediatek,mt8163-rng", "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_TRNG>; + clock-names = "rng"; + }; + gic: interrupt-controller@10221000 { compatible = "arm,gic-400"; reg = <0 0x10221000 0 0x1000>, From ef76663ec6cf858c15d0a215005e4977e0d161fc Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Mon, 9 Feb 2026 16:51:49 +0000 Subject: [PATCH 063/126] ASoC: mediatek: Add ASoC driver for MT8163 AFE Add an ASoC driver for the AFE (Audio Front End) on the MT8163 SoC. Currently only the I2S DAIs are implemented. Signed-off-by: Ben Grisdale --- sound/soc/mediatek/Kconfig | 10 + sound/soc/mediatek/Makefile | 1 + sound/soc/mediatek/mt8163/Makefile | 9 + sound/soc/mediatek/mt8163/mt8163-afe-clk.c | 342 +++++++ sound/soc/mediatek/mt8163/mt8163-afe-clk.h | 40 + sound/soc/mediatek/mt8163/mt8163-afe-common.h | 122 +++ sound/soc/mediatek/mt8163/mt8163-afe-pcm.c | 790 +++++++++++++++ sound/soc/mediatek/mt8163/mt8163-afe-regs.h | 378 +++++++ sound/soc/mediatek/mt8163/mt8163-dai-i2s.c | 926 ++++++++++++++++++ 9 files changed, 2618 insertions(+) create mode 100644 sound/soc/mediatek/mt8163/Makefile create mode 100644 sound/soc/mediatek/mt8163/mt8163-afe-clk.c create mode 100644 sound/soc/mediatek/mt8163/mt8163-afe-clk.h create mode 100644 sound/soc/mediatek/mt8163/mt8163-afe-common.h create mode 100644 sound/soc/mediatek/mt8163/mt8163-afe-pcm.c create mode 100644 sound/soc/mediatek/mt8163/mt8163-afe-regs.h create mode 100644 sound/soc/mediatek/mt8163/mt8163-dai-i2s.c diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig index 3a1e1fa3fe5cc7..2ac79bc1faa7ca 100644 --- a/sound/soc/mediatek/Kconfig +++ b/sound/soc/mediatek/Kconfig @@ -76,6 +76,16 @@ config SND_SOC_MT7986_WM8960 Select Y if you have such device. If unsure select "N". +config SND_SOC_MT8163 + tristate "ASoC support for Mediatek MT8163 chip" + depends on ARCH_MEDIATEK + select SND_SOC_MEDIATEK + help + This adds ASoC platform driver support for Mediatek MT8163 chip + that can be used with other codecs. + Select Y if you have such device. + Ex: MT8163 + config SND_SOC_MT8173 tristate "ASoC support for Mediatek MT8173 chip" depends on ARCH_MEDIATEK diff --git a/sound/soc/mediatek/Makefile b/sound/soc/mediatek/Makefile index 7cd67bce92e9a4..81a337d450fa44 100644 --- a/sound/soc/mediatek/Makefile +++ b/sound/soc/mediatek/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_SND_SOC_MEDIATEK) += common/ obj-$(CONFIG_SND_SOC_MT2701) += mt2701/ obj-$(CONFIG_SND_SOC_MT6797) += mt6797/ obj-$(CONFIG_SND_SOC_MT7986) += mt7986/ +obj-$(CONFIG_SND_SOC_MT8163) += mt8163/ obj-$(CONFIG_SND_SOC_MT8173) += mt8173/ obj-$(CONFIG_SND_SOC_MT8183) += mt8183/ obj-$(CONFIG_SND_SOC_MT8186) += mt8186/ diff --git a/sound/soc/mediatek/mt8163/Makefile b/sound/soc/mediatek/mt8163/Makefile new file mode 100644 index 00000000000000..14db8ab957e2d5 --- /dev/null +++ b/sound/soc/mediatek/mt8163/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 + +# Platform Driver +snd-soc-mt8163-afe-y := \ + mt8163-afe-clk.o \ + mt8163-afe-pcm.o \ + mt8163-dai-i2s.o + +obj-$(CONFIG_SND_SOC_MT8163) += snd-soc-mt8163-afe.o diff --git a/sound/soc/mediatek/mt8163/mt8163-afe-clk.c b/sound/soc/mediatek/mt8163/mt8163-afe-clk.c new file mode 100644 index 00000000000000..6fb13936808f5f --- /dev/null +++ b/sound/soc/mediatek/mt8163/mt8163-afe-clk.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek MT8163 ALSA SoC Audio AFE clock control + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include + +#include "mt8163-afe-regs.h" +#include "mt8163-afe-common.h" +#include "mt8163-afe-clk.h" + +#define MT8163_APLL1_RATE 90316800 +#define MT8163_APLL2_RATE 98304000 + +static const char *mt8163_afe_base_clks[MT8163_BASE_CLK_NUM] = { + [MT8163_BASE_CLK_INFRASYS_AUD] = "infrasys_aud", + [MT8163_BASE_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_bus", + [MT8163_BASE_CLK_TOP_PDN_AUD] = "top_pdn_aud", + [MT8163_BASE_CLK_TOP_I2S] = "top_i2s", + [MT8163_BASE_CLK_AFE] = "afe", + [MT8163_BASE_CLK_ADC] = "adc", + [MT8163_BASE_CLK_DAC] = "dac", + [MT8163_BASE_CLK_DAC_PREDIS] = "dac_predis", +}; + +static const char *mt8163_afe_misc_clks[MT8163_MISC_CLK_NUM] = { + [MT8163_MISC_CLK_APLL1] = "apll1", + [MT8163_MISC_CLK_APLL1_TUNER] = "apll1_tuner", + [MT8163_MISC_CLK_APLL2] = "apll2", + [MT8163_MISC_CLK_APLL2_TUNER] = "apll2_tuner", + [MT8163_MISC_CLK_22M] = "22m", + [MT8163_MISC_CLK_24M] = "24m", + [MT8163_MISC_CLK_APLL1_DIV] = "apll1_div", + [MT8163_MISC_CLK_APLL2_DIV] = "apll2_div", + [MT8163_MISC_CLK_AUD_1_SEL] = "aud_1_sel", + [MT8163_MISC_CLK_AUD_2_SEL] = "aud_2_sel", + [MT8163_MISC_CLK_I2S0] = "i2s0", + [MT8163_MISC_CLK_I2S1] = "i2s1", + [MT8163_MISC_CLK_I2S2] = "i2s2", + [MT8163_MISC_CLK_I2S3] = "i2s3", + [MT8163_MISC_CLK_CLK26M] = "clk26m", +}; + +int mt8163_init_clock(struct mtk_base_afe *afe) +{ + struct mt8163_afe_private *priv = afe->platform_priv; + int i, ret; + + for (i = 0; i < MT8163_BASE_CLK_NUM; i++) + priv->base_clocks[i].id = mt8163_afe_base_clks[i]; + for (i = 0; i < MT8163_MISC_CLK_NUM; i++) + priv->misc_clocks[i].id = mt8163_afe_misc_clks[i]; + + ret = devm_clk_bulk_get(afe->dev, MT8163_BASE_CLK_NUM, priv->base_clocks); + if (ret) { + dev_err(afe->dev, "Failed to get AFE base clocks: %d.\n", ret); + return ret; + } + + ret = devm_clk_bulk_get(afe->dev, MT8163_MISC_CLK_NUM, priv->misc_clocks); + if (ret) { + dev_err(afe->dev, "Failed to get AFE misc clocks: %d.\n", ret); + return ret; + } + + return 0; +} + +int mt8163_afe_enable_clock(struct mtk_base_afe *afe) +{ + struct mt8163_afe_private *priv = afe->platform_priv; + int ret; + + /* Bulk prepare and enable base clocks. */ + ret = clk_bulk_prepare_enable(MT8163_BASE_CLK_NUM, priv->base_clocks); + if (ret) { + dev_err(afe->dev, "Failed to enable base clocks: %d.\n", ret); + return ret; + } + + return 0; +} + +void mt8163_afe_disable_clock(struct mtk_base_afe *afe) +{ + struct mt8163_afe_private *priv = afe->platform_priv; + + clk_bulk_disable_unprepare(MT8163_BASE_CLK_NUM, priv->base_clocks); +} + +int mt8163_apll1_enable(struct mtk_base_afe *afe) +{ + struct mt8163_afe_private *priv = afe->platform_priv; + int ret; + + /* Make sure APLL is prepared and enabled. */ + ret = clk_prepare_enable(priv->misc_clocks[MT8163_MISC_CLK_APLL1].clk); + if (ret) { + dev_err(afe->dev, "Failed to enable APLL1: %d.\n", ret); + return ret; + } + + /* + * Set the APLL to a predetermined rate, none of the dividers set + * CLK_SET_RATE_PARENT since we want to avoid changing the PLL rate + * from what we set initially. + */ + ret = clk_set_rate(priv->misc_clocks[MT8163_MISC_CLK_APLL1].clk, + MT8163_APLL1_RATE); + if (ret) { + dev_err(afe->dev, "Failed to set APLL1 rate: %d.\n", ret); + return ret; + } + + /* Switch the top audio muxes to PLL source. */ + ret = clk_set_parent(priv->misc_clocks[MT8163_MISC_CLK_AUD_1_SEL].clk, + priv->misc_clocks[MT8163_MISC_CLK_APLL1].clk); + if (ret) { + dev_err(afe->dev, "Failed to reparent audio clock to PLL: %d.\n", ret); + return ret; + } + + /* Enable and set the APLL divider to /4. */ + ret = clk_prepare_enable(priv->misc_clocks[MT8163_MISC_CLK_APLL1_DIV].clk); + if (ret) { + dev_err(afe->dev, "Failed to enable APLL1 divider: %d.\n", ret); + return ret; + } + + ret = clk_set_rate(priv->misc_clocks[MT8163_MISC_CLK_APLL1_DIV].clk, + (MT8163_APLL1_RATE >> 2)); + if (ret) { + dev_err(afe->dev, "Failed to set APLL1 divider rate: %d.\n", ret); + return ret; + } + + /* Enable top 22M clock */ + ret = clk_prepare_enable(priv->misc_clocks[MT8163_MISC_CLK_22M].clk); + if (ret) { + dev_err(afe->dev, "Failed to enable 22M clock: %d.\n", ret); + return ret; + } + + /* Enable APLL1 tuner */ + ret = clk_prepare_enable(priv->misc_clocks[MT8163_MISC_CLK_APLL1_TUNER].clk); + if (ret) { + dev_err(afe->dev, "Failed to enable APLL1 tuner: %d.\n", ret); + return ret; + } + + /* Set APLL1 tuner configuration */ + regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, + 0x0000FFF7, 0x00008033); + + return 0; +} + +void mt8163_apll1_disable(struct mtk_base_afe *afe) +{ + struct mt8163_afe_private *priv = afe->platform_priv; + int ret; + + /* Reparent audio mux to clk26m */ + ret = clk_set_parent(priv->misc_clocks[MT8163_MISC_CLK_AUD_1_SEL].clk, + priv->misc_clocks[MT8163_MISC_CLK_CLK26M].clk); + if (ret) { + dev_err(afe->dev, "Failed to reparent audio clock to clk26m: %d.\n", ret); + } + + clk_disable_unprepare(priv->misc_clocks[MT8163_MISC_CLK_APLL1_DIV].clk); + clk_disable_unprepare(priv->misc_clocks[MT8163_MISC_CLK_APLL1].clk); + clk_disable_unprepare(priv->misc_clocks[MT8163_MISC_CLK_APLL1_TUNER].clk); + clk_disable_unprepare(priv->misc_clocks[MT8163_MISC_CLK_22M].clk); +} + +int mt8163_apll2_enable(struct mtk_base_afe *afe) +{ + struct mt8163_afe_private *priv = afe->platform_priv; + int ret; + + /* Make sure APLL2 is prepared and enabled. */ + ret = clk_prepare_enable(priv->misc_clocks[MT8163_MISC_CLK_APLL2].clk); + if (ret) { + dev_err(afe->dev, "Failed to enable APLL2: %d.\n", ret); + return ret; + } + + /* + * Set the APLL to a predetermined rate, none of the dividers set + * CLK_SET_RATE_PARENT since we want to avoid changing the PLL rate + * from what we set initially. + */ + ret = clk_set_rate(priv->misc_clocks[MT8163_MISC_CLK_APLL2].clk, + MT8163_APLL2_RATE); + if (ret) { + dev_err(afe->dev, "Failed to set APLL1 rate: %d.\n", ret); + return ret; + } + + /* Switch the top audio muxes to PLL source. */ + ret = clk_set_parent(priv->misc_clocks[MT8163_MISC_CLK_AUD_2_SEL].clk, + priv->misc_clocks[MT8163_MISC_CLK_APLL2].clk); + if (ret) { + dev_err(afe->dev, "Failed to reparent audio clock to PLL: %d.\n", ret); + return ret; + } + + /* Enable and set the APLL2 divider to /4. */ + ret = clk_prepare_enable(priv->misc_clocks[MT8163_MISC_CLK_APLL2_DIV].clk); + if (ret) { + dev_err(afe->dev, "Failed to enable APLL2 divider: %d.\n", ret); + return ret; + } + + ret = clk_set_rate(priv->misc_clocks[MT8163_MISC_CLK_APLL2_DIV].clk, + (MT8163_APLL2_RATE >> 2)); + if (ret) { + dev_err(afe->dev, "Failed to set APLL2 divider rate: %d.\n", ret); + return ret; + } + + /* Enable top 24M clock */ + ret = clk_prepare_enable(priv->misc_clocks[MT8163_MISC_CLK_24M].clk); + if (ret) { + dev_err(afe->dev, "Failed to enable 24M clock: %d.\n", ret); + return ret; + } + + /* Enable APLL2 tuner */ + ret = clk_prepare_enable(priv->misc_clocks[MT8163_MISC_CLK_APLL2_TUNER].clk); + if (ret) { + dev_err(afe->dev, "Failed to enable APLL2 tuner: %d.\n", ret); + return ret; + } + + /* Set APLL2 tuner configuration */ + regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, + 0x0000FFF7, 0x00000435); + + return 0; +} + +void mt8163_apll2_disable(struct mtk_base_afe *afe) +{ + struct mt8163_afe_private *priv = afe->platform_priv; + int ret; + + /* Reparent audio mux to clk26m */ + ret = clk_set_parent(priv->misc_clocks[MT8163_MISC_CLK_AUD_2_SEL].clk, + priv->misc_clocks[MT8163_MISC_CLK_CLK26M].clk); + if (ret) { + dev_err(afe->dev, "Failed to reparent audio clock to clk26m: %d.\n", ret); + } + + clk_disable_unprepare(priv->misc_clocks[MT8163_MISC_CLK_APLL2_DIV].clk); + clk_disable_unprepare(priv->misc_clocks[MT8163_MISC_CLK_APLL2].clk); + clk_disable_unprepare(priv->misc_clocks[MT8163_MISC_CLK_APLL2_TUNER].clk); + clk_disable_unprepare(priv->misc_clocks[MT8163_MISC_CLK_24M].clk); +} + +int mt8163_get_apll_rate(int apll) +{ + return (apll == MT8163_APLL1) ? MT8163_APLL1_RATE : MT8163_APLL2_RATE; +} + +int mt8163_get_apll_by_rate(int rate) +{ + if (!(MT8163_APLL1_RATE % rate)) + return MT8163_APLL1; + else if (!(MT8163_APLL2_RATE % rate)) + return MT8163_APLL2; + else + return -1; +} + +int mt8163_get_apll_by_name(const char *name) +{ + if (strcmp(name, APLL1_W_NAME) == 0) + return MT8163_APLL1; + else + return MT8163_APLL2; +} + +/* mck */ +static const int mck_clks[MT8163_MCK_NUM] = { + [MT8163_I2S0_MCK] = MT8163_MISC_CLK_I2S0, + [MT8163_I2S1_MCK] = MT8163_MISC_CLK_I2S1, + [MT8163_I2S2_MCK] = MT8163_MISC_CLK_I2S2, + [MT8163_I2S3_MCK] = MT8163_MISC_CLK_I2S3, +}; + +int mt8163_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate) +{ + struct mt8163_afe_private *afe_priv = afe->platform_priv; + int apll = mt8163_get_apll_by_rate(rate); + int apll_clk_id = apll == MT8163_APLL1 ? + MT8163_MISC_CLK_AUD_1_SEL : MT8163_MISC_CLK_AUD_2_SEL; + int i2s_clk_id = mck_clks[mck_id]; + int ret; + + if (apll < 0) + return -EINVAL; + + /* Enable divider and select PLL */ + ret = clk_prepare_enable(afe_priv->misc_clocks[i2s_clk_id].clk); + if (ret) { + dev_err(afe->dev, "Failed to enable I2S clock %s: %d.\n", + mt8163_afe_misc_clks[i2s_clk_id], ret); + return ret; + } + ret = clk_set_parent(afe_priv->misc_clocks[i2s_clk_id].clk, + afe_priv->misc_clocks[apll_clk_id].clk); + if (ret) { + dev_err(afe->dev, "Failed to reparent I2S clock %s to PLL %s: %d.\n", + mt8163_afe_misc_clks[i2s_clk_id], + mt8163_afe_misc_clks[apll_clk_id], ret); + goto disable_i2s_clk; + } + + /* Set rate, change divider */ + ret = clk_set_rate(afe_priv->misc_clocks[i2s_clk_id].clk, rate); + if (ret) { + dev_err(afe->dev, "Failed to set rate for I2S clock %s: %d.\n", + mt8163_afe_misc_clks[i2s_clk_id], ret); + goto disable_i2s_clk; + } + + return 0; + +disable_i2s_clk: + clk_disable_unprepare(afe_priv->misc_clocks[i2s_clk_id].clk); + return ret; +} + +void mt8163_mck_disable(struct mtk_base_afe *afe, int mck_id) +{ + struct mt8163_afe_private *afe_priv = afe->platform_priv; + int i2s_clk_id = mck_clks[mck_id]; + + clk_disable_unprepare(afe_priv->misc_clocks[i2s_clk_id].clk); +} diff --git a/sound/soc/mediatek/mt8163/mt8163-afe-clk.h b/sound/soc/mediatek/mt8163/mt8163-afe-clk.h new file mode 100644 index 00000000000000..b7761860bb7a84 --- /dev/null +++ b/sound/soc/mediatek/mt8163/mt8163-afe-clk.h @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek MT8163 AFE ASoC platform driver. + * Copyright (c) 2025-2026 Ben Grisdale + * + * based on: sound/soc/mediatek/mt8183/mt8183-afe-clk.h + * Copyright (c) 2018 MediaTek Inc. + * Author: KaiChieh Chuang + */ + +#ifndef _MT8163_AFE_CLK_H_ +#define _MT8163_AFE_CLK_H_ + +/* APLL */ +#define APLL1_W_NAME "APLL1" +#define APLL2_W_NAME "APLL2" +enum { + MT8163_APLL1 = 0, + MT8163_APLL2, +}; + +struct mtk_base_afe; + +int mt8163_init_clock(struct mtk_base_afe *afe); +int mt8163_afe_enable_clock(struct mtk_base_afe *afe); +void mt8163_afe_disable_clock(struct mtk_base_afe *afe); + +int mt8163_apll1_enable(struct mtk_base_afe *afe); +void mt8163_apll1_disable(struct mtk_base_afe *afe); + +int mt8163_apll2_enable(struct mtk_base_afe *afe); +void mt8163_apll2_disable(struct mtk_base_afe *afe); + +int mt8163_get_apll_rate(int apll); +int mt8163_get_apll_by_rate(int rate); +int mt8163_get_apll_by_name(const char *name); + +int mt8163_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate); +void mt8163_mck_disable(struct mtk_base_afe *afe, int mck_id); +#endif diff --git a/sound/soc/mediatek/mt8163/mt8163-afe-common.h b/sound/soc/mediatek/mt8163/mt8163-afe-common.h new file mode 100644 index 00000000000000..0da72839a2d86b --- /dev/null +++ b/sound/soc/mediatek/mt8163/mt8163-afe-common.h @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek MT8163 AFE ASoC platform driver. + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#ifndef _MT8163_AFE_COMMON_H_ +#define _MT8163_AFE_COMMON_H_ + +#include +#include +#include +#include +#include "../common/mtk-base-afe.h" + +#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ + SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_176400 |\ + SNDRV_PCM_RATE_192000) + +#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +/* Various providing clocks to AFE */ +enum { + MT8163_BASE_CLK_INFRASYS_AUD = 0, + MT8163_BASE_CLK_TOP_PDN_AUD_BUS, + MT8163_BASE_CLK_TOP_PDN_AUD, + MT8163_BASE_CLK_TOP_I2S, + MT8163_BASE_CLK_AFE, + MT8163_BASE_CLK_ADC, + MT8163_BASE_CLK_DAC, + MT8163_BASE_CLK_DAC_PREDIS, + MT8163_BASE_CLK_NUM, +}; + +enum { + MT8163_MISC_CLK_APLL1 = 0, + MT8163_MISC_CLK_APLL1_TUNER, + MT8163_MISC_CLK_APLL2, + MT8163_MISC_CLK_APLL2_TUNER, + MT8163_MISC_CLK_22M, + MT8163_MISC_CLK_24M, + MT8163_MISC_CLK_APLL1_DIV, + MT8163_MISC_CLK_APLL2_DIV, + MT8163_MISC_CLK_AUD_1_SEL, + MT8163_MISC_CLK_AUD_2_SEL, + MT8163_MISC_CLK_I2S0, + MT8163_MISC_CLK_I2S1, + MT8163_MISC_CLK_I2S2, + MT8163_MISC_CLK_I2S3, + MT8163_MISC_CLK_CLK26M, + MT8163_MISC_CLK_NUM +}; + +/* MCLK */ +enum { + MT8163_I2S0_MCK = 0, + MT8163_I2S1_MCK, + MT8163_I2S2_MCK, + MT8163_I2S3_MCK, + MT8163_MCK_NUM, +}; + +/* Digital blocks on SoC */ +enum { + /* Memory Interfaces (MEMIF) */ + MT8163_AFE_MEMIF_DL1 = 0, + MT8163_AFE_MEMIF_DL2, + MT8163_AFE_MEMIF_VUL, + MT8163_AFE_MEMIF_AWB, + /* I2S memif is not a real memif. */ + MT8163_AFE_MEMIF_I2S, + MT8163_AFE_MEMIF_NUM, + + /* Digital Audio Interfaces (DAI) */ +#if 0 // TODO: implement PCM support? + MT8163_AFE_DAI_PCM1 = MT8163_AFE_MEMIF_NUM, + MT8163_AFE_DAI_PCM2, + MT8163_AFE_DAI_I2S0, +#else + MT8163_AFE_DAI_I2S0 = MT8163_AFE_MEMIF_NUM, +#endif + MT8163_AFE_DAI_I2S1, + MT8163_AFE_DAI_I2S2, + MT8163_AFE_DAI_I2S3, +#if 0 // TODO: implement hw gain support? + MT8163_AFE_DAI_HW_GAIN1, + MT8163_AFE_DAI_HW_GAIN2, +#endif + MT8163_AFE_DAI_NUM, +}; + +enum { + MT8163_AFE_IRQ1_MCU = 0, + MT8163_AFE_IRQ2_MCU, + MT8163_AFE_IRQ5_MCU, + MT8163_AFE_IRQ7_MCU, + MT8163_AFE_IRQ_NUM, +}; + +struct mt8163_afe_private { + /* clocks */ + struct clk_bulk_data base_clocks[MT8163_BASE_CLK_NUM]; + struct clk_bulk_data misc_clocks[MT8163_MISC_CLK_NUM]; + + /* dai */ + void *dai_priv[MT8163_AFE_DAI_NUM]; +}; + +int mt8163_general_rate_transform(unsigned int rate); + +int mt8163_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name, + const char *secondary_i2s_name); + +/* dai register */ +int mt8163_dai_pcm_register(struct mtk_base_afe *afe); +int mt8163_dai_i2s_register(struct mtk_base_afe *afe); + +#endif /* _MT8163_AFE_COMMON_H_ */ diff --git a/sound/soc/mediatek/mt8163/mt8163-afe-pcm.c b/sound/soc/mediatek/mt8163/mt8163-afe-pcm.c new file mode 100644 index 00000000000000..9f073761ad9141 --- /dev/null +++ b/sound/soc/mediatek/mt8163/mt8163-afe-pcm.c @@ -0,0 +1,790 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek MT8163 AFE ASoC platform driver. + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mt8163-afe-common.h" +#include "mt8163-afe-clk.h" +#include "mt8163-afe-regs.h" +#include "../common/mtk-afe-platform-driver.h" +#include "../common/mtk-afe-fe-dai.h" + +enum { + MT8163_AFE_RATE_8K = 0, + MT8163_AFE_RATE_11K = 1, + MT8163_AFE_RATE_12K = 2, + MT8163_AFE_RATE_16K = 4, + MT8163_AFE_RATE_22K = 5, + MT8163_AFE_RATE_24K = 6, + MT8163_AFE_RATE_32K = 8, + MT8163_AFE_RATE_44K = 9, + MT8163_AFE_RATE_48K = 10, + MT8163_AFE_RATE_88K = 11, + MT8163_AFE_RATE_96K = 12, + MT8163_AFE_RATE_174K = 13, + MT8163_AFE_RATE_192K = 14, + MT8163_AFE_RATE_260K = 15, +}; + +static const unsigned int mt8163_afe_backup_list[] = { + AUDIO_TOP_CON1, + AUDIO_TOP_CON2, + AUDIO_TOP_CON3, + AFE_DAC_CON0, + AFE_DAC_CON1, + AFE_I2S_CON, + AFE_DAIBT_CON0, + AFE_CONN0, + AFE_CONN1, + AFE_CONN2, + AFE_CONN3, + AFE_CONN4, + AFE_I2S_CON1, + AFE_I2S_CON2, + AFE_MRGIF_CON, + AFE_DL1_BASE, + AFE_DL1_CUR, + AFE_DL1_END, + AFE_DL1_D2_BASE, + AFE_DL1_D2_CUR, + AFE_DL1_D2_END, + AFE_VUL_D2_BASE, + AFE_VUL_D2_END, + AFE_VUL_D2_CUR, + AFE_I2S_CON3, + AFE_DL2_BASE, + AFE_DL2_CUR, + AFE_DL2_END, + AFE_CONN5, + AFE_CONN_24BIT, + AFE_AWB_BASE, + AFE_AWB_END, + AFE_AWB_CUR, + AFE_VUL_BASE, + AFE_VUL_END, + AFE_VUL_CUR, + AFE_DAI_BASE, + AFE_DAI_END, + AFE_DAI_CUR, + AFE_CONN6, + AFE_MEMIF_MSB, + AFE_ADDA_DL_SRC2_CON0, + AFE_ADDA_DL_SRC2_CON1, + AFE_ADDA_UL_SRC_CON0, + AFE_ADDA_UL_SRC_CON1, + AFE_ADDA_TOP_CON0, + AFE_ADDA_UL_DL_CON0, + AFE_ADDA_NEWIF_CFG0, + AFE_ADDA_NEWIF_CFG1, + AFE_SIDETONE_CON0, + AFE_SIDETONE_COEFF, + AFE_SIDETONE_CON1, + AFE_SIDETONE_GAIN, + AFE_SGEN_CON0, + AFE_TOP_CON0, + AFE_ADDA_PREDIS_CON0, + AFE_ADDA_PREDIS_CON1, + AFE_MOD_DAI_BASE, + AFE_MOD_DAI_END, + AFE_MOD_DAI_CUR, + AFE_IRQ_MCU_CON, + AFE_IRQ_MCU_CNT1, + AFE_IRQ_MCU_CNT2, + AFE_IRQ_MCU_EN, + AFE_MEMIF_MAXLEN, + AFE_MEMIF_PBUF_SIZE, + AFE_IRQ_MCU_CNT7, + AFE_APLL1_TUNER_CFG, + AFE_APLL2_TUNER_CFG, + AFE_GAIN1_CON0, + AFE_GAIN1_CON1, + AFE_GAIN1_CON2, + AFE_GAIN1_CON3, + AFE_GAIN1_CONN, + AFE_GAIN1_CUR, + AFE_GAIN2_CON0, + AFE_GAIN2_CON1, + AFE_GAIN2_CON2, + AFE_GAIN2_CON3, + AFE_GAIN2_CONN, + AFE_GAIN2_CUR, + AFE_GAIN2_CONN2, + AFE_GAIN2_CONN3, + AFE_GAIN1_CONN2, + AFE_GAIN1_CONN3, + AFE_CONN7, + AFE_CONN8, + AFE_CONN9, + AFE_CONN10, + FPGA_CFG2, + FPGA_CFG3, + FPGA_CFG0, + FPGA_CFG1, + AFE_ASRC_CON0, + AFE_ASRC_CON1, + AFE_ASRC_CON2, + AFE_ASRC_CON3, + AFE_ASRC_CON4, + AFE_ASRC_CON5, + AFE_ASRC_CON6, + AFE_ASRC_CON7, + AFE_ASRC_CON8, + AFE_ASRC_CON9, + AFE_ASRC_CON10, + AFE_ASRC_CON11, + PCM_INTF_CON1, + PCM_INTF_CON2, + PCM2_INTF_CON, + AUDIO_CLK_AUDDIV_0, + AUDIO_CLK_AUDDIV_1, + AFE_ASRC4_CON0, + AFE_ASRC4_CON1, + AFE_ASRC4_CON2, + AFE_ASRC4_CON3, + AFE_ASRC4_CON4, + AFE_ASRC4_CON5, + AFE_ASRC4_CON6, + AFE_ASRC4_CON7, + AFE_ASRC4_CON8, + AFE_ASRC4_CON9, + AFE_ASRC4_CON10, + AFE_ASRC4_CON11, + AFE_ASRC4_CON12, + AFE_ASRC4_CON13, + AFE_ASRC4_CON14, + AFE_ASRC_CON13, + AFE_ASRC_CON14, + AFE_ASRC_CON15, + AFE_ASRC_CON16, + AFE_ASRC_CON17, + AFE_ASRC_CON18, + AFE_ASRC_CON19, + AFE_ASRC_CON20, + AFE_ASRC_CON21, + AFE_ASRC2_CON0, + AFE_ASRC2_CON1, + AFE_ASRC2_CON2, + AFE_ASRC2_CON3, + AFE_ASRC2_CON4, + AFE_ASRC2_CON5, + AFE_ASRC2_CON6, + AFE_ASRC2_CON7, + AFE_ASRC2_CON8, + AFE_ASRC2_CON9, + AFE_ASRC2_CON10, + AFE_ASRC2_CON11, + AFE_ASRC2_CON12, + AFE_ASRC2_CON13, + AFE_ASRC2_CON14, + AFE_ASRC3_CON0, + AFE_ASRC3_CON1, + AFE_ASRC3_CON2, + AFE_ASRC3_CON3, + AFE_ASRC3_CON4, + AFE_ASRC3_CON5, + AFE_ASRC3_CON6, + AFE_ASRC3_CON7, + AFE_ASRC3_CON8, + AFE_ASRC3_CON9, + AFE_ASRC3_CON10, + AFE_ASRC3_CON11, + AFE_ASRC3_CON12, + AFE_ASRC3_CON13, + AFE_ASRC3_CON14, + AFE_ADDA4_TOP_CON0, + AFE_ADDA4_UL_SRC_CON0, + AFE_ADDA4_UL_SRC_CON1, + AFE_ADDA4_NEWIF_CFG0, + AFE_ADDA4_NEWIF_CFG1, + AFE_ADDA4_ULCF_CFG_02_01, + AFE_ADDA4_ULCF_CFG_04_03, + AFE_ADDA4_ULCF_CFG_06_05, + AFE_ADDA4_ULCF_CFG_08_07, + AFE_ADDA4_ULCF_CFG_10_09, + AFE_ADDA4_ULCF_CFG_12_11, + AFE_ADDA4_ULCF_CFG_14_13, + AFE_ADDA4_ULCF_CFG_16_15, + AFE_ADDA4_ULCF_CFG_18_17, + AFE_ADDA4_ULCF_CFG_20_19, + AFE_ADDA4_ULCF_CFG_22_21, + AFE_ADDA4_ULCF_CFG_24_23, + AFE_ADDA4_ULCF_CFG_26_25, + AFE_ADDA4_ULCF_CFG_28_27, + AFE_ADDA4_ULCF_CFG_30_29, +}; + +int mt8163_general_rate_transform(unsigned int rate) +{ + switch (rate) { + case 8000: + return MT8163_AFE_RATE_8K; + case 11025: + return MT8163_AFE_RATE_11K; + case 12000: + return MT8163_AFE_RATE_12K; + case 16000: + return MT8163_AFE_RATE_16K; + case 22050: + return MT8163_AFE_RATE_22K; + case 24000: + return MT8163_AFE_RATE_24K; + case 32000: + return MT8163_AFE_RATE_32K; + case 44100: + return MT8163_AFE_RATE_44K; + case 48000: + return MT8163_AFE_RATE_48K; + case 88000: + return MT8163_AFE_RATE_88K; + case 96000: + return MT8163_AFE_RATE_96K; + case 174000: + return MT8163_AFE_RATE_174K; + case 192000: + return MT8163_AFE_RATE_192K; + case 260000: + return MT8163_AFE_RATE_260K; + default: + return -EINVAL; + } +} + +static const struct snd_pcm_hardware mt8163_afe_hardware = { + .info = SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_MMAP_VALID, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, + .period_bytes_min = 256, + .period_bytes_max = 4 * 48 * 1024, + .periods_min = 2, + .periods_max = 256, + .buffer_bytes_max = 8 * 48 * 1024, + .fifo_size = 0, +}; + +static int mt8163_memif_fs(struct snd_pcm_substream *substream, + unsigned int rate) +{ + return mt8163_general_rate_transform(rate); +} + +static int mt8163_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) +{ + return mt8163_general_rate_transform(rate); +} + +#define MT8163_DAI_MEMIF_DL(_name) { \ + .name = #_name, \ + .id = MT8163_AFE_MEMIF_##_name, \ + .playback = { \ + .stream_name = #_name, \ + .channels_min = 1, \ + .channels_max = 2, \ + .rates = MTK_PCM_RATES, \ + .formats = MTK_PCM_FORMATS \ + }, \ + .ops = &mtk_afe_fe_ops, \ +} + +#define MT8163_DAI_MEMIF_UL(_name) { \ + .name = #_name, \ + .id = MT8163_AFE_MEMIF_##_name, \ + .capture = { \ + .stream_name = #_name, \ + .channels_min = 1, \ + .channels_max = 2, \ + .rates = MTK_PCM_RATES, \ + .formats = MTK_PCM_FORMATS \ + }, \ + .ops = &mtk_afe_fe_ops, \ +} + +static struct snd_soc_dai_driver mt8163_memif_dai_driver[] = { + /* FE DAIs: memory intefaces to CPU */ + MT8163_DAI_MEMIF_DL(DL1), + MT8163_DAI_MEMIF_DL(DL2), + MT8163_DAI_MEMIF_UL(VUL), + MT8163_DAI_MEMIF_UL(AWB), +}; + +/* dma widget & routes*/ +static const struct snd_kcontrol_new memif_vul_ch1_mix[] = { + /* I00 - O09 */ + SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN5, 8, 1, 0), + /* I03 - O09 */ + SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN3, 0, 1, 0), +}; + +static const struct snd_kcontrol_new memif_vul_ch2_mix[] = { + /* I01 - O10 */ + SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN5, 13, 1, 0), + /* I04 - O10 */ + SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN3, 3, 1, 0), +}; + +static const struct snd_kcontrol_new memif_awb_ch1_mix[] = { + /* I00 - O05 */ + SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN2, 16, 1, 0), + /* I05 - O05 */ + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN2, 19, 1, 0), + /* I15 - O05 */ + SOC_DAPM_SINGLE_AUTODISABLE("MRG_CH1", AFE_CONN4, 6, 1, 0), +}; + +static const struct snd_kcontrol_new memif_awb_ch2_mix[] = { + /* I01 - O06 */ + SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN2, 22, 1, 0), + /* I06 - O06 */ + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN2, 24, 1, 0), + /* I16 - O06 */ + SOC_DAPM_SINGLE_AUTODISABLE("MRG_CH2", AFE_CONN4, 8, 1, 0), +}; + +static const struct snd_soc_dapm_widget mt8163_memif_widgets[] = { + /* memif */ + SND_SOC_DAPM_MIXER("VUL_CH1", SND_SOC_NOPM, 0, 0, + memif_vul_ch1_mix, ARRAY_SIZE(memif_vul_ch1_mix)), + SND_SOC_DAPM_MIXER("VUL_CH2", SND_SOC_NOPM, 0, 0, + memif_vul_ch2_mix, ARRAY_SIZE(memif_vul_ch2_mix)), + SND_SOC_DAPM_MIXER("AWB_CH1", SND_SOC_NOPM, 0, 0, + memif_awb_ch1_mix, ARRAY_SIZE(memif_awb_ch1_mix)), + SND_SOC_DAPM_MIXER("AWB_CH2", SND_SOC_NOPM, 0, 0, + memif_awb_ch2_mix, ARRAY_SIZE(memif_awb_ch2_mix)), +}; + +static const struct snd_soc_dapm_route mt8163_memif_routes[] = { + /* capture */ + {"AWB", NULL, "AWB_CH1"}, + {"AWB", NULL, "AWB_CH2"}, + {"AWB_CH1", "I2S0_CH1", "I2S0"}, + {"AWB_CH2", "I2S0_CH2", "I2S0"}, + + {"VUL", NULL, "VUL_CH1"}, + {"VUL", NULL, "VUL_CH2"}, + {"VUL_CH1", "I2S2_CH1", "I2S2"}, + {"VUL_CH2", "I2S2_CH2", "I2S2"}, +}; + +static const struct snd_soc_component_driver mt8163_afe_pcm_dai_component = { + .name = "mt8163-afe-pcm-dai", +}; + +/* Dummy register / field definitions */ +#define NO_ENABLE -1 +#define NO_MODE -1 +#define NO_MONO -1 +#define MOD_DAI_DATA_SHIFT -1 +#define DAI_DATA_SHIFT -1 +#define MOD_DAI_PBUF_SIZE_SHIFT 0 +#define MOD_DAI_PBUF_SIZE_MASK 0 +#define DAI_PBUF_SIZE_SHIFT 0 +#define DAI_PBUF_SIZE_MASK 0 +#define AWB_PBUF_SIZE_SHIFT 0 +#define AWB_PBUF_SIZE_MASK 0 +#define VUL_PBUF_SIZE_SHIFT 0 +#define VUL_PBUF_SIZE_MASK 0 + +#define MT8163_MEMIF_BASE(_id, _en_reg, _fs_reg, _mono_reg, \ + _pbuf_reg) \ + [MT8163_AFE_MEMIF_##_id] = { \ + .name = #_id, \ + .id = MT8163_AFE_MEMIF_##_id, \ + .reg_ofs_base = AFE_##_id##_BASE, \ + .reg_ofs_cur = AFE_##_id##_CUR, \ + .reg_ofs_end = AFE_##_id##_END, \ + .fs_reg = _fs_reg, \ + .fs_shift = _id##_MODE_SHIFT, \ + .fs_maskbit = _id##_MODE_MASK, \ + .mono_reg = _mono_reg, \ + .mono_shift = _id##_DATA_SHIFT, \ + .enable_reg = _en_reg, \ + .enable_shift = _id##_ON_SHIFT, \ + .hd_reg = _pbuf_reg, \ + .hd_align_reg = _pbuf_reg, \ + .hd_shift = _id##_HD_SHIFT, \ + .hd_align_mshift = _id##_HD_ALIGN_SHIFT, \ + .agent_disable_reg = -1, \ + .agent_disable_shift = -1, \ + .msb_reg = AFE_MEMIF_MSB, \ + .msb_shift = _id##_MSB_SHIFT, \ + .pbuf_reg = _pbuf_reg, \ + .pbuf_mask = _id##_PBUF_SIZE_MASK, \ + .pbuf_shift = _id##_PBUF_SIZE_SHIFT, \ + } + +#define MT8163_MEMIF(_id, _fs_reg, _mono_reg, _pbuf_reg) \ + MT8163_MEMIF_BASE(_id, AFE_DAC_CON0, _fs_reg, _mono_reg, _pbuf_reg) + +static const struct mtk_base_memif_data memif_data[MT8163_AFE_MEMIF_NUM] = { + MT8163_MEMIF(DL1, AFE_DAC_CON1, AFE_DAC_CON1, AFE_MEMIF_PBUF_SIZE), + MT8163_MEMIF(DL2, AFE_DAC_CON1, AFE_DAC_CON1, AFE_MEMIF_PBUF_SIZE), + MT8163_MEMIF(VUL, AFE_DAC_CON1, AFE_DAC_CON1, AFE_MEMIF_PBUF_SIZE), + MT8163_MEMIF(AWB, AFE_DAC_CON1, AFE_DAC_CON1, AFE_MEMIF_PBUF_SIZE), +}; + +#define MT8163_AFE_IRQ(_id, _cnt_reg, _fs_reg, _fs_shift, \ + _en_shift, _clr_shift) \ + [MT8163_AFE_##_id] = { \ + .id = MT8163_AFE_##_id, \ + .irq_cnt_reg = _cnt_reg, \ + .irq_cnt_shift = 0, \ + .irq_cnt_maskbit = (_cnt_reg < 0 ? -1 : 0x3ffff), \ + .irq_fs_reg = _fs_reg, \ + .irq_fs_shift = _fs_shift, \ + .irq_fs_maskbit = (_fs_reg < 0 ? -1 : 0xf), \ + .irq_en_reg = AFE_IRQ_MCU_CON, \ + .irq_en_shift = _en_shift, \ + .irq_clr_reg = AFE_IRQ_MCU_CLR, \ + .irq_clr_shift = _clr_shift, \ + } + +static const struct mtk_base_irq_data irq_data[MT8163_AFE_IRQ_NUM] = { + MT8163_AFE_IRQ(IRQ1_MCU, AFE_IRQ_MCU_CNT1, AFE_IRQ_MCU_CON, 4, 0, 0), + MT8163_AFE_IRQ(IRQ2_MCU, AFE_IRQ_MCU_CNT2, AFE_IRQ_MCU_CON, 8, 1, 1), + MT8163_AFE_IRQ(IRQ5_MCU, AFE_IRQ_MCU_CNT5, -1, -1, 12, 4), + MT8163_AFE_IRQ(IRQ7_MCU, AFE_IRQ_MCU_CNT7, AFE_IRQ_MCU_CON, 24, 14, 6), +}; + +/* Maps MEMIF to IRQ_MCU usage */ +static const int memif_irq_usage[MT8163_AFE_MEMIF_NUM] = { + [MT8163_AFE_MEMIF_DL1] = MT8163_AFE_IRQ1_MCU, + [MT8163_AFE_MEMIF_DL2] = MT8163_AFE_IRQ7_MCU, + [MT8163_AFE_MEMIF_VUL] = MT8163_AFE_IRQ2_MCU, + [MT8163_AFE_MEMIF_AWB] = MT8163_AFE_IRQ2_MCU, +}; + +static const struct regmap_config mt8163_afe_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = AFE_MAXLENGTH, + .cache_type = REGCACHE_NONE, +}; + +static irqreturn_t mt8163_afe_irq_handler(int irq_id, void *dev) +{ + struct mtk_base_afe *afe = dev; + struct mtk_base_afe_irq *irq; + unsigned int status; + unsigned int status_mcu; + unsigned int mcu_en; + int ret; + int i; + irqreturn_t irq_ret = IRQ_HANDLED; + + /* Get the IRQs that are sent to MCU */ + ret = regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en); + if (ret) { + dev_err(afe->dev, "Failed to read AFE_IRQ_MCU_EN register: %d.\n", ret); + status_mcu = AFE_IRQ_MCU_STATUS_BITS; + goto err_irq; + } + + ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status); + if (ret) { + dev_err(afe->dev, "Failed to read AFE_IRQ_MCU_STATUS register: %d.\n", ret); + status_mcu = AFE_IRQ_MCU_STATUS_BITS; + goto err_irq; + } + + /* Mask off irrelevant bits - we only care about status */ + status_mcu = status & AFE_IRQ_MCU_STATUS_BITS; + + if (ret || status_mcu == 0) { + dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n", + __func__, ret, status, mcu_en); + + irq_ret = IRQ_NONE; + goto err_irq; + } + + for (i = 0; i < MT8163_AFE_MEMIF_NUM; i++) { + struct mtk_base_afe_memif *memif = &afe->memif[i]; + + if (!memif->substream) + continue; + + if (memif->irq_usage < 0) + continue; + + irq = &afe->irqs[memif->irq_usage]; + + /* + * Check if the IRQ isn't enabled and if so clear the bits off the + * status, to avoid clearing non-MCU interrupts. We need to do it this + * way because the control and status bits for each IRQ between the status + * and enable register are different, so we can't just use the value of the + * AFE_IRQ_MCU_EN register as mask like other SoCs do. + */ + if (!(mcu_en & BIT(irq->irq_data->irq_en_shift))) { + status_mcu &= ~BIT(irq->irq_data->irq_clr_shift); + continue; + } + + if (status_mcu & BIT(irq->irq_data->irq_clr_shift)) + snd_pcm_period_elapsed(memif->substream); + } + +err_irq: + /* clear irq */ + regmap_write(afe->regmap, + AFE_IRQ_MCU_CLR, + status_mcu); + + return irq_ret; +} + +static int mt8163_afe_runtime_suspend(struct device *dev) +{ + struct mtk_base_afe *afe = dev_get_drvdata(dev); + + regmap_clear_bits(afe->regmap, AFE_DAC_CON0, AFE_ON); + mt8163_afe_disable_clock(afe); + return 0; +} + +static int mt8163_afe_runtime_resume(struct device *dev) +{ + struct mtk_base_afe *afe = dev_get_drvdata(dev); + int ret; + + ret = mt8163_afe_enable_clock(afe); + if (ret) + return ret; + + /* set APB 3.0 */ + regmap_set_bits(afe->regmap, AUDIO_TOP_CON0, APB3_SEL); + + /* enable AFE */ + regmap_set_bits(afe->regmap, AFE_DAC_CON0, AFE_ON); + + return 0; +} + +static int mt8163_dai_memif_register(struct mtk_base_afe *afe) +{ + struct mtk_base_afe_dai *dai; + + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); + if (!dai) + return -ENOMEM; + + list_add(&dai->list, &afe->sub_dais); + + dai->dai_drivers = mt8163_memif_dai_driver; + dai->num_dai_drivers = ARRAY_SIZE(mt8163_memif_dai_driver); + + dai->dapm_widgets = mt8163_memif_widgets; + dai->num_dapm_widgets = ARRAY_SIZE(mt8163_memif_widgets); + dai->dapm_routes = mt8163_memif_routes; + dai->num_dapm_routes = ARRAY_SIZE(mt8163_memif_routes); + return 0; +} + +typedef int (*dai_register_cb)(struct mtk_base_afe *); +static const dai_register_cb dai_register_cbs[] = { + mt8163_dai_i2s_register, + mt8163_dai_memif_register, +}; + +static int mt8163_afe_pcm_dev_probe(struct platform_device *pdev) +{ + struct mtk_base_afe *afe; + struct mt8163_afe_private *afe_priv; + struct device *dev = &pdev->dev; + int i, irq_id, ret; + + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) + return ret; + + afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); + if (!afe) + return -ENOMEM; + platform_set_drvdata(pdev, afe); + + afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), GFP_KERNEL); + if (!afe->platform_priv) + return -ENOMEM; + + afe_priv = afe->platform_priv; + afe->dev = dev; + + ret = of_reserved_mem_device_init(dev); + if (ret) { + dev_info(dev, "no reserved memory found, pre-allocating buffers instead\n"); + afe->preallocate_buffers = true; + } + + /* initial audio related clock */ + ret = mt8163_init_clock(afe); + if (ret) { + dev_err(dev, "init clock error\n"); + return ret; + } + + /* regmap init */ + afe->regmap = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(afe->regmap)) { + dev_err(dev, "could not get regmap from parent\n"); + ret = PTR_ERR(afe->regmap); + goto err_pm_disable; + } + + ret = regmap_attach_dev(dev, afe->regmap, &mt8163_afe_regmap_config); + if (ret) { + dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret); + goto err_pm_disable; + } + + /* init memif */ + afe->memif_size = MT8163_AFE_MEMIF_NUM; + afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), + GFP_KERNEL); + if (!afe->memif) { + ret = -ENOMEM; + goto err_pm_disable; + } + + for (i = 0; i < afe->memif_size; i++) { + afe->memif[i].data = &memif_data[i]; + afe->memif[i].irq_usage = memif_irq_usage[i]; + afe->memif[i].const_irq = 1; + } + + mutex_init(&afe->irq_alloc_lock); + + /* irq initialize */ + afe->irqs_size = MT8163_AFE_IRQ_NUM; + afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), + GFP_KERNEL); + if (!afe->irqs) { + ret = -ENOMEM; + goto err_pm_disable; + } + + for (i = 0; i < afe->irqs_size; i++) + afe->irqs[i].irq_data = &irq_data[i]; + + /* request irq */ + irq_id = platform_get_irq(pdev, 0); + if (irq_id < 0) { + ret = irq_id; + goto err_pm_disable; + } + + ret = devm_request_irq(dev, irq_id, mt8163_afe_irq_handler, + IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); + if (ret) { + dev_err(dev, "could not request_irq for asys-isr\n"); + goto err_pm_disable; + } + + /* init sub_dais */ + INIT_LIST_HEAD(&afe->sub_dais); + + for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { + ret = dai_register_cbs[i](afe); + if (ret) { + dev_warn(dev, "dai register i %d fail, ret %d\n", + i, ret); + goto err_pm_disable; + } + } + + /* init dai_driver and component_driver */ + ret = mtk_afe_combine_sub_dai(afe); + if (ret) { + dev_warn(dev, "mtk_afe_combine_sub_dai fail, ret %d\n", ret); + goto err_pm_disable; + } + + afe->mtk_afe_hardware = &mt8163_afe_hardware; + afe->memif_fs = mt8163_memif_fs; + afe->irq_fs = mt8163_irq_fs; + + pm_runtime_enable(dev); + if (!pm_runtime_enabled(dev)) { + ret = mt8163_afe_runtime_resume(dev); + if (ret) + goto err_pm_disable; + } + + afe->reg_back_up_list = mt8163_afe_backup_list; + afe->reg_back_up_list_num = ARRAY_SIZE(mt8163_afe_backup_list); + + afe->runtime_resume = mt8163_afe_runtime_resume; + afe->runtime_suspend = mt8163_afe_runtime_suspend; + + /* register component */ + ret = devm_snd_soc_register_component(dev, &mtk_afe_pcm_platform, + NULL, 0); + if (ret) { + dev_warn(dev, "err_platform\n"); + goto err_pm_disable; + } + + ret = devm_snd_soc_register_component(dev, &mt8163_afe_pcm_dai_component, + afe->dai_drivers, + afe->num_dai_drivers); + if (ret) { + dev_warn(dev, "err_dai_component\n"); + goto err_pm_disable; + } + + return ret; + +err_pm_disable: + pm_runtime_disable(dev); + return ret; +} + +static void mt8163_afe_pcm_dev_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + snd_soc_unregister_component(dev); + + pm_runtime_disable(dev); + if (!pm_runtime_status_suspended(dev)) + mt8163_afe_runtime_suspend(dev); +} + +static const struct of_device_id mt8163_afe_pcm_dt_match[] = { + { .compatible = "mediatek,mt8163-afe-pcm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mt8163_afe_pcm_dt_match); + +static const struct dev_pm_ops mt8163_afe_pm_ops = { + RUNTIME_PM_OPS(mt8163_afe_runtime_suspend, + mt8163_afe_runtime_resume, NULL) +}; + +static struct platform_driver mt8163_afe_pcm_driver = { + .driver = { + .name = "mt8163-afe-pcm", + .of_match_table = mt8163_afe_pcm_dt_match, + .pm = pm_ptr(&mt8163_afe_pm_ops), + }, + .probe = mt8163_afe_pcm_dev_probe, + .remove = mt8163_afe_pcm_dev_remove, +}; + +module_platform_driver(mt8163_afe_pcm_driver); + +MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver"); +MODULE_AUTHOR("Ben Grisdale "); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/mediatek/mt8163/mt8163-afe-regs.h b/sound/soc/mediatek/mt8163/mt8163-afe-regs.h new file mode 100644 index 00000000000000..6d625f11a86506 --- /dev/null +++ b/sound/soc/mediatek/mt8163/mt8163-afe-regs.h @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek MT8163 AFE ASoC platform driver. + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#ifndef _MT8163_AFE_REGS_H +#define _MT8163_AFE_REGS_H + +/* Register definitions */ +#define AUDIO_TOP_CON0 0x0000 +#define AUDIO_TOP_CON1 0x0004 +#define AUDIO_TOP_CON2 0x0008 +#define AUDIO_TOP_CON3 0x000C +#define AFE_DAC_CON0 0x0010 +#define AFE_DAC_CON1 0x0014 +#define AFE_I2S_CON 0x0018 +#define AFE_DAIBT_CON0 0x001c +#define AFE_CONN0 0x0020 +#define AFE_CONN1 0x0024 +#define AFE_CONN2 0x0028 +#define AFE_CONN3 0x002C +#define AFE_CONN4 0x0030 +#define AFE_I2S_CON1 0x0034 +#define AFE_I2S_CON2 0x0038 +#define AFE_MRGIF_CON 0x003C +#define AFE_DL1_BASE 0x0040 +#define AFE_DL1_CUR 0x0044 +#define AFE_DL1_END 0x0048 +#define AFE_DL1_D2_BASE 0x0340 +#define AFE_DL1_D2_CUR 0x0344 +#define AFE_DL1_D2_END 0x0348 +#define AFE_VUL_D2_BASE 0x0350 +#define AFE_VUL_D2_END 0x0358 +#define AFE_VUL_D2_CUR 0x035C +#define AFE_I2S_CON3 0x004C +#define AFE_DL2_BASE 0x0050 +#define AFE_DL2_CUR 0x0054 +#define AFE_DL2_END 0x0058 +#define AFE_CONN5 0x005C +#define AFE_CONN_24BIT 0x006C +#define AFE_AWB_BASE 0x0070 +#define AFE_AWB_END 0x0078 +#define AFE_AWB_CUR 0x007C +#define AFE_VUL_BASE 0x0080 +#define AFE_VUL_END 0x0088 +#define AFE_VUL_CUR 0x008C +#define AFE_DAI_BASE 0x0090 +#define AFE_DAI_END 0x0098 +#define AFE_DAI_CUR 0x009C +#define AFE_CONN6 0x00BC +#define AFE_MEMIF_MSB 0x00CC +#define AFE_MEMIF_MON0 0x00D0 +#define AFE_MEMIF_MON1 0x00D4 +#define AFE_MEMIF_MON2 0x00D8 +#define AFE_MEMIF_MON4 0x00E0 +#define AFE_ADDA_DL_SRC2_CON0 0x0108 +#define AFE_ADDA_DL_SRC2_CON1 0x010C +#define AFE_ADDA_UL_SRC_CON0 0x0114 +#define AFE_ADDA_UL_SRC_CON1 0x0118 +#define AFE_ADDA_TOP_CON0 0x0120 +#define AFE_ADDA_UL_DL_CON0 0x0124 +#define AFE_ADDA_SRC_DEBUG 0x012C +#define AFE_ADDA_SRC_DEBUG_MON0 0x0130 +#define AFE_ADDA_SRC_DEBUG_MON1 0x0134 +#define AFE_ADDA_NEWIF_CFG0 0x0138 +#define AFE_ADDA_NEWIF_CFG1 0x013C +#define AFE_SIDETONE_DEBUG 0x01D0 +#define AFE_SIDETONE_MON 0x01D4 +#define AFE_SIDETONE_CON0 0x01E0 +#define AFE_SIDETONE_COEFF 0x01E4 +#define AFE_SIDETONE_CON1 0x01E8 +#define AFE_SIDETONE_GAIN 0x01EC +#define AFE_SGEN_CON0 0x01F0 +#define AFE_TOP_CON0 0x0200 +#define AFE_ADDA_PREDIS_CON0 0x0260 +#define AFE_ADDA_PREDIS_CON1 0x0264 +#define AFE_MRGIF_MON0 0x0270 +#define AFE_MRGIF_MON1 0x0274 +#define AFE_MRGIF_MON2 0x0278 +#define AFE_MOD_DAI_BASE 0x0330 +#define AFE_MOD_DAI_END 0x0338 +#define AFE_MOD_DAI_CUR 0x033C +#define AFE_HDMI_OUT_CON0 0x0370 +#define AFE_HDMI_BASE 0x0374 +#define AFE_HDMI_CUR 0x0378 +#define AFE_HDMI_END 0x037C +#define AFE_SPDIF_OUT_CON0 0x0380 +#define AFE_SPDIF_BASE 0x0384 +#define AFE_SPDIF_CUR 0x0388 +#define AFE_SPDIF_END 0x038C +#define AFE_HDMI_CONN0 0x0390 +#define AFE_HDMI_CONN1 0x0398 +#define AFE_IRQ_MCU_CON 0x03A0 +#define AFE_IRQ_MCU_STATUS 0x03A4 +#define AFE_IRQ_MCU_CLR 0x03A8 +#define AFE_IRQ_MCU_CNT1 0x03AC +#define AFE_IRQ_MCU_CNT2 0x03B0 +#define AFE_IRQ_MCU_EN 0x03B4 +#define AFE_IRQ_MCU_MON2 0x03B8 +#define AFE_IRQ_MCU_CNT5 0x03BC +#define AFE_IRQ1_MCU_CNT_MON 0x03C0 +#define AFE_IRQ2_MCU_CNT_MON 0x03C4 +#define AFE_IRQ1_MCU_EN_CNT_MON 0x03C8 +#define AFE_IRQ_DEBUG 0x03CC +#define AFE_MEMIF_MINLEN 0x03D0 +#define AFE_MEMIF_MAXLEN 0x03D4 +#define AFE_MEMIF_PBUF_SIZE 0x03D8 +#define AFE_IRQ_MCU_CNT7 0x03DC +#define AFE_APLL1_TUNER_CFG 0x03f0 +#define AFE_APLL2_TUNER_CFG 0x03f4 +#define AFE_GAIN1_CON0 0x0410 +#define AFE_GAIN1_CON1 0x0414 +#define AFE_GAIN1_CON2 0x0418 +#define AFE_GAIN1_CON3 0x041C +#define AFE_GAIN1_CONN 0x0420 +#define AFE_GAIN1_CUR 0x0424 +#define AFE_GAIN2_CON0 0x0428 +#define AFE_GAIN2_CON1 0x042C +#define AFE_GAIN2_CON2 0x0430 +#define AFE_GAIN2_CON3 0x0434 +#define AFE_GAIN2_CONN 0x0438 +#define AFE_GAIN2_CUR 0x043C +#define AFE_GAIN2_CONN2 0x0440 +#define AFE_GAIN2_CONN3 0x0444 +#define AFE_GAIN1_CONN2 0x0448 +#define AFE_GAIN1_CONN3 0x044C +#define AFE_CONN7 0x0460 +#define AFE_CONN8 0x0464 +#define AFE_CONN9 0x0468 +#define AFE_CONN10 0x046C +#define AFE_IEC_CFG 0x0480 +#define AFE_IEC_NSNUM 0x0484 +#define AFE_IEC_BURST_INFO 0x0488 +#define AFE_IEC_BURST_LEN 0x048C +#define AFE_IEC_NSADR 0x0490 +#define AFE_IEC_CHL_STAT0 0x04A0 +#define AFE_IEC_CHL_STAT1 0x04A4 +#define AFE_IEC_CHR_STAT0 0x04A8 +#define AFE_IEC_CHR_STAT1 0x04AC +#define FPGA_CFG2 0x04B8 +#define FPGA_CFG3 0x04BC +#define FPGA_CFG0 0x04C0 +#define FPGA_CFG1 0x04C4 +#define FPGA_VER 0x04C8 +#define FPGA_STC 0x04CC +#define AFE_ASRC_CON0 0x0500 +#define AFE_ASRC_CON1 0x0504 +#define AFE_ASRC_CON2 0x0508 +#define AFE_ASRC_CON3 0x050C +#define AFE_ASRC_CON4 0x0510 +#define AFE_ASRC_CON5 0x0514 +#define AFE_ASRC_CON6 0x0518 +#define AFE_ASRC_CON7 0x051C +#define AFE_ASRC_CON8 0x0520 +#define AFE_ASRC_CON9 0x0524 +#define AFE_ASRC_CON10 0x0528 +#define AFE_ASRC_CON11 0x052C +#define PCM_INTF_CON1 0x0530 +#define PCM_INTF_CON2 0x0538 +#define PCM2_INTF_CON 0x053C +#define AFE_TDM_CON1 0x0548 +#define AFE_TDM_CON2 0x054C +#define AFE_ASRC_CON13 0x0550 +#define AFE_ASRC_CON14 0x0554 +#define AFE_ASRC_CON15 0x0558 +#define AFE_ASRC_CON16 0x055C +#define AFE_ASRC_CON17 0x0560 +#define AFE_ASRC_CON18 0x0564 +#define AFE_ASRC_CON19 0x0568 +#define AFE_ASRC_CON20 0x056C +#define AFE_ASRC_CON21 0x0570 +#define AUDIO_CLK_AUDDIV_0 0x05A0 +#define AUDIO_CLK_AUDDIV_1 0x05A4 +#define AFE_ASRC4_CON0 0x06C0 +#define AFE_ASRC4_CON1 0x06C4 +#define AFE_ASRC4_CON2 0x06C8 +#define AFE_ASRC4_CON3 0x06CC +#define AFE_ASRC4_CON4 0x06D0 +#define AFE_ASRC4_CON5 0x06D4 +#define AFE_ASRC4_CON6 0x06D8 +#define AFE_ASRC4_CON7 0x06DC +#define AFE_ASRC4_CON8 0x06E0 +#define AFE_ASRC4_CON9 0x06E4 +#define AFE_ASRC4_CON10 0x06E8 +#define AFE_ASRC4_CON11 0x06EC +#define AFE_ASRC4_CON12 0x06F0 +#define AFE_ASRC4_CON13 0x06F4 +#define AFE_ASRC4_CON14 0x06F8 +#define AFE_ASRC2_CON0 0x0700 +#define AFE_ASRC2_CON1 0x0704 +#define AFE_ASRC2_CON2 0x0708 +#define AFE_ASRC2_CON3 0x070C +#define AFE_ASRC2_CON4 0x0710 +#define AFE_ASRC2_CON5 0x0714 +#define AFE_ASRC2_CON6 0x0718 +#define AFE_ASRC2_CON7 0x071C +#define AFE_ASRC2_CON8 0x0720 +#define AFE_ASRC2_CON9 0x0724 +#define AFE_ASRC2_CON10 0x0728 +#define AFE_ASRC2_CON11 0x072C +#define AFE_ASRC2_CON12 0x0730 +#define AFE_ASRC2_CON13 0x0734 +#define AFE_ASRC2_CON14 0x0738 +#define AFE_ASRC3_CON0 0x0740 +#define AFE_ASRC3_CON1 0x0744 +#define AFE_ASRC3_CON2 0x0748 +#define AFE_ASRC3_CON3 0x074C +#define AFE_ASRC3_CON4 0x0750 +#define AFE_ASRC3_CON5 0x0754 +#define AFE_ASRC3_CON6 0x0758 +#define AFE_ASRC3_CON7 0x075C +#define AFE_ASRC3_CON8 0x0760 +#define AFE_ASRC3_CON9 0x0764 +#define AFE_ASRC3_CON10 0x0768 +#define AFE_ASRC3_CON11 0x076C +#define AFE_ASRC3_CON12 0x0770 +#define AFE_ASRC3_CON13 0x0774 +#define AFE_ASRC3_CON14 0x0778 +#define AFE_ADDA4_TOP_CON0 0x0780 +#define AFE_ADDA4_UL_SRC_CON0 0x0784 +#define AFE_ADDA4_UL_SRC_CON1 0x0788 +#define AFE_ADDA4_SRC_DEBUG 0x078C +#define AFE_ADDA4_SRC_DEBUG_MON0 0x0790 +#define AFE_ADDA4_SRC_DEBUG_MON1 0x0794 +#define AFE_ADDA4_NEWIF_CFG0 0x0798 +#define AFE_ADDA4_NEWIF_CFG1 0x079C +#define AFE_ADDA4_ULCF_CFG_02_01 0x07A0 +#define AFE_ADDA4_ULCF_CFG_04_03 0x07A4 +#define AFE_ADDA4_ULCF_CFG_06_05 0x07A8 +#define AFE_ADDA4_ULCF_CFG_08_07 0x07AC +#define AFE_ADDA4_ULCF_CFG_10_09 0x07B0 +#define AFE_ADDA4_ULCF_CFG_12_11 0x07B4 +#define AFE_ADDA4_ULCF_CFG_14_13 0x07B8 +#define AFE_ADDA4_ULCF_CFG_16_15 0x07BC +#define AFE_ADDA4_ULCF_CFG_18_17 0x07C0 +#define AFE_ADDA4_ULCF_CFG_20_19 0x07C4 +#define AFE_ADDA4_ULCF_CFG_22_21 0x07C8 +#define AFE_ADDA4_ULCF_CFG_24_23 0x07CC +#define AFE_ADDA4_ULCF_CFG_26_25 0x07D0 +#define AFE_ADDA4_ULCF_CFG_28_27 0x07D4 +#define AFE_ADDA4_ULCF_CFG_30_29 0x07D8 +#define AFE_MAXLENGTH 0x07D8 + +/* Register field definitions */ + +/* IRQ MCU status bits */ +#define AFE_IRQ_MCU_STATUS_BITS (GENMASK(1, 0) | GENMASK(7, 4)) + +/* Control register for I2S Slave/Master */ +#define AFE_I2S_S_I2S_EN_SHIFT 0 +#define AFE_I2S_S_I2S_WLEN BIT(1) +#define AFE_I2S_S_I2S_SRC BIT(2) +#define AFE_I2S_S_I2S_FMT BIT(3) +#define AFE_I2S_S_INV_LRCK BIT(5) +#define AFE_I2S_S_INV_PAD_CTRL BIT(7) +#define AFE_I2S_S_I2S_HD_EN_SHIFT 12 +#define AFE_I2S_S_I2S_LOOPBACK BIT(20) +#define AFE_I2S_S_I2SIN_PAD_SEL BIT(28) +#define AFE_I2S_S_BCK_INV BIT(29) +#define AFE_I2S_S_BCK_NEG_EG_LATCH BIT(30) +#define AFE_I2S_S_PHASE_SHIFT_FIX BIT(31) + +/* Control register for I2S Master only */ +#define AFE_I2S_M_I2S_EN_SHIFT 0 +#define AFE_I2S_M_I2S_WLEN BIT(1) +#define AFE_I2S_M_I2S_FMT BIT(3) +#define AFE_I2S_M_INV_LRCK BIT(5) +#define AFE_I2S_M_I2S_OUT_MODE GENMASK(11, 8) +#define AFE_I2S_M_I2S_HD_EN_SHIFT 12 +#define AFE_I2S_M_I2S_LR_SWAP BIT(31) + +/* AUDIO_TOP_CON0 fields */ +#define APB3_SEL BIT(14) + +/* AFE_DAC_CON0 fields */ +#define AWB_RETM_SHIFT 31 +#define DL1_D2_RETM_SHIFT 30 +#define DL2_RETM_SHIFT 29 +#define DL1_RETM_SHIFT 28 +#define ON_RETM_SHIFT 27 +#define MOD_DAI_DUP_WR_SHIFT 26 +#define DAI_MODE_SHIFT 24 +#define DAI_MODE_MASK GENMASK(1, 0) +#define VUL_D2_MODE_SHIFT 20 +#define VUL_D2_MODE_MASK GENMASK(3, 0) +#define DL1_D2_MODE_SHIFT 16 +#define DL2_D2_MODE_MASK GENMASK(3, 0) +#define VUL2_R_MONO_SHIFT 11 +#define VUL2_DATA_SHIFT 10 +#define VUL_D2_ON_SHIFT 9 +#define DL1_D2_ON_SHIFT 8 +#define MOD_DAI_ON_SHIFT 7 +#define AWB_ON_SHIFT 6 +#define DAI_ON_SHIFT 4 +#define VUL_ON_SHIFT 3 +#define DL2_ON_SHIFT 2 +#define DL1_ON_SHIFT 1 +#define AFE_ON BIT(0) + +/* AFE_DAC_CON1 fields */ +#define MOD_DAI_MODE_SHIFT 30 +#define MOD_DAI_MODE_MASK GENMASK(1, 0) +#define DAI_DUP_WR_SHIFT 29 +#define VUL_R_MONO_SHIFT 28 +#define VUL_DATA_SHIFT 27 +#define AXI_2X1_CG_DISABLE_SHIFT 26 +#define AWB_R_MONO_SHIFT 25 +#define AWB_DATA_SHIFT 24 +#define DL2_DATA_SHIFT 22 +#define DL1_DATA_SHIFT 21 +#define DL1_D2_DATA_SHIFT 20 +#define VUL_MODE_SHIFT 16 +#define VUL_MODE_MASK GENMASK(3, 0) +#define AWB_MODE_SHIFT 12 +#define AWB_MODE_MASK GENMASK(3, 0) +#define I2S_MODE_SHIFT 8 +#define I2S_MODE_MASK GENMASK(3, 0) +#define I2S_MODE_MASK_SHIFT (I2S_MODE_MASK << I2S_MODE_SHIFT) +#define DL2_MODE_SHIFT 4 +#define DL2_MODE_MASK GENMASK(3, 0) +#define DL1_MODE_SHIFT 0 +#define DL1_MODE_MASK GENMASK(3, 0) + +/* AFE_MEMIF_PBUF_SIZE fields */ +#define SPDIF_HD_ALIGN_SHIFT 31 +#define SPDIF_HD_SHIFT 30 +#define HDMI_HD_ALIGN_SHIFT 29 +#define HDMI_HD_SHIFT 28 +#define MOD_DAI_HD_ALIGN_SHIFT 27 +#define MOD_DAI_HD_SHIFT 26 +#define DAI_HD_ALIGN_SHIFT 25 +#define DAI_HD_SHIFT 24 +#define VUL_HD_ALIGN_SHIFT 23 +#define VUL_HD_SHIFT 22 +#define AWB_HD_ALIGN_SHIFT 21 +#define AWB_HD_SHIFT 20 +#define DL2_HD_ALIGN_SHIFT 19 +#define DL2_HD_SHIFT 18 +#define DL1_HD_ALIGN_SHIFT 17 +#define DL1_HD_SHIFT 16 +#define VUL_D2_HD_ALIGN_SHIFT 15 +#define VUL_D2_HD_SHIFT 14 +#define DL1_D2_HD_ALIGN_SHIFT 13 +#define DL1_D2_HD_SHIFT 12 +#define DL1_D2_4CH_SHIFT 11 +#define VUL_D2_4CH_SHIFT 10 +#define DL1_D2_PBUF_SIZE_SHIFT 8 +#define DL1_D2_PBUF_SIZE_MASK GENMASK(1, 0) +#define IEC_PBUF_SIZE_SHIFT 6 +#define IEC_PBUF_SIZE_MASK GENMASK(1, 0) +#define HDMI_PBUF_SIZE_SHIFT 4 +#define HDMI_PBUF_SIZE_MASK GENMASK(1, 0) +#define DL2_PBUF_SIZE_SHIFT 2 +#define DL2_PBUF_SIZE_MASK GENMASK(1, 0) +#define DL1_PBUF_SIZE_SHIFT 0 +#define DL1_PBUF_SIZE_MASK GENMASK(1, 0) + +/* AFE_MEMIF_PBUF2_SIZE fields */ +#define SPDIF2_HD_ALIGN_SHIFT 3 +#define SPDIF2_HD_SHIFT 2 +#define IEC2_PBUF_SIZE_SHIFT 0 +#define IEC2_PBUF_SIZE_MASK GENMASK(1, 0) + +/* AFE_MEMIF_MSB fields */ +#define SPDIF2_MSB_SHIFT 10 +#define SPDIF_MSB_SHIFT 9 +#define HDMI_MSB_SHIFT 8 +#define VUL2_D2_MSB_SHIFT 7 +#define VUL_MSB_SHIFT 6 +#define DAI_MSB_SHIFT 5 +#define MOD_DAI_MSB_SHIFT 4 +#define AWB_MSB_SHIFT 3 +#define DL1_D2_MSB_SHIFT 2 +#define DL2_MSB_SHIFT 1 +#define DL1_MSB_SHIFT 0 + +#endif /* _MT8163_AFE_REGS_H */ diff --git a/sound/soc/mediatek/mt8163/mt8163-dai-i2s.c b/sound/soc/mediatek/mt8163/mt8163-dai-i2s.c new file mode 100644 index 00000000000000..d4e4160eefc5bb --- /dev/null +++ b/sound/soc/mediatek/mt8163/mt8163-dai-i2s.c @@ -0,0 +1,926 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek MT8163 AFE ASoC platform driver. + * Copyright (c) 2025-2026 Ben Grisdale + * + * based on: sound/soc/mediatek/mt8183/mt8183-dai-i2s.c + * Copyright (c) 2018 MediaTek Inc. + * Author: KaiChieh Chuang + */ + +#include +#include +#include +#include "mt8163-afe-clk.h" +#include "mt8163-afe-common.h" +#include "mt8163-afe-regs.h" + +enum { + I2S_WLEN_16_BIT = 0, + I2S_WLEN_32_BIT = 1, +}; + +enum { + I2S_IN_PAD_CONNSYS = 0, + I2S_IN_PAD_IO_MUX = 1, +}; + +struct mtk_afe_i2s_priv { + int id; + int rate; /* to determine which apll to use */ + int low_jitter_en; + + int share_i2s_id; + + int mclk_id; + int mclk_rate; + int mclk_apll; + + bool use_i2s; + + u32 con_reg; + u32 output_fmt_bits; +}; + +static unsigned int get_i2s_wlen(snd_pcm_format_t format) +{ + return snd_pcm_format_physical_width(format) <= 16 ? + I2S_WLEN_16_BIT : I2S_WLEN_32_BIT; +} + +#define MT8163_AFE_I2S0_KCONTROL_NAME "I2S0_HD_Mux" +#define MT8163_AFE_I2S1_KCONTROL_NAME "I2S1_HD_Mux" +#define MT8163_AFE_I2S2_KCONTROL_NAME "I2S2_HD_Mux" +#define MT8163_AFE_I2S3_KCONTROL_NAME "I2S3_HD_Mux" + +#define I2S0_HD_EN_W_NAME "I2S0_HD_EN" +#define I2S1_HD_EN_W_NAME "I2S1_HD_EN" +#define I2S2_HD_EN_W_NAME "I2S2_HD_EN" +#define I2S3_HD_EN_W_NAME "I2S3_HD_EN" + +#define I2S0_MCLK_EN_W_NAME "I2S0_MCLK_EN" +#define I2S1_MCLK_EN_W_NAME "I2S1_MCLK_EN" +#define I2S2_MCLK_EN_W_NAME "I2S2_MCLK_EN" +#define I2S3_MCLK_EN_W_NAME "I2S3_MCLK_EN" + +static int get_i2s_id_by_name(struct mtk_base_afe *afe, + const char *name) +{ + if (strncmp(name, "I2S0", 4) == 0) + return MT8163_AFE_DAI_I2S0; + else if (strncmp(name, "I2S1", 4) == 0) + return MT8163_AFE_DAI_I2S1; + else if (strncmp(name, "I2S2", 4) == 0) + return MT8163_AFE_DAI_I2S2; + else if (strncmp(name, "I2S3", 4) == 0) + return MT8163_AFE_DAI_I2S3; + else { + WARN_ONCE(1, "Invalid I2S name: %s", name); + return -EINVAL; + } +} + +static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe, + const char *name) +{ + struct mt8163_afe_private *afe_priv = afe->platform_priv; + int dai_id = get_i2s_id_by_name(afe, name); + + if (dai_id < 0) + return NULL; + + return afe_priv->dai_priv[dai_id]; +} + +/* low jitter control */ +static const char * const mt8163_i2s_hd_str[] = { + "Normal", "Low_Jitter" +}; + +static const struct soc_enum mt8163_i2s_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8163_i2s_hd_str), + mt8163_i2s_hd_str), +}; + +static int mt8163_i2s_hd_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + + i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); + + if (!i2s_priv) + return -EINVAL; + + ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en; + + return 0; +} + +static int mt8163_i2s_hd_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + int hd_en, change; + + if (ucontrol->value.enumerated.item[0] >= e->items) + return -EINVAL; + + hd_en = ucontrol->value.integer.value[0]; + + i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); + + if (!i2s_priv) + return -EINVAL; + + change = i2s_priv->low_jitter_en != hd_en; + i2s_priv->low_jitter_en = hd_en; + + return change; +} + +static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = { + SOC_ENUM_EXT(MT8163_AFE_I2S0_KCONTROL_NAME, mt8163_i2s_enum[0], + mt8163_i2s_hd_get, mt8163_i2s_hd_set), + SOC_ENUM_EXT(MT8163_AFE_I2S1_KCONTROL_NAME, mt8163_i2s_enum[0], + mt8163_i2s_hd_get, mt8163_i2s_hd_set), + SOC_ENUM_EXT(MT8163_AFE_I2S2_KCONTROL_NAME, mt8163_i2s_enum[0], + mt8163_i2s_hd_get, mt8163_i2s_hd_set), + SOC_ENUM_EXT(MT8163_AFE_I2S3_KCONTROL_NAME, mt8163_i2s_enum[0], + mt8163_i2s_hd_get, mt8163_i2s_hd_set), +}; + +/* dai component */ +/* interconnection */ +static const struct snd_kcontrol_new mtk_i2s3_ch1_mix[] = { + /* I05 - O00 */ + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN0, 5, 1, 0), + /* I07 - O00 */ + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN0, 7, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2s3_ch2_mix[] = { + /* I06 - O01 */ + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN0, 22, 1, 0), + /* I08 - O01 */ + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN0, 24, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2s1_ch1_mix[] = { + /* I05 - O03 */ + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN1, 21, 1, 0), + /* I07 - O03 */ + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN1, 23, 1, 0), +}; + +static const struct snd_kcontrol_new mtk_i2s1_ch2_mix[] = { + /* I06 - O04 */ + SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN2, 6, 1, 0), + /* I08 - O04 */ + SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN2, 8, 1, 0), +}; + +enum { + SUPPLY_SEQ_APLL, + SUPPLY_SEQ_I2S_MCLK_EN, + SUPPLY_SEQ_I2S_HD_EN, + SUPPLY_SEQ_I2S_EN, +}; + +static int mtk_apll_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (snd_soc_dapm_widget_name_cmp(w, APLL1_W_NAME) == 0) + mt8163_apll1_enable(afe); + else + mt8163_apll2_enable(afe); + break; + case SND_SOC_DAPM_POST_PMD: + if (snd_soc_dapm_widget_name_cmp(w, APLL1_W_NAME) == 0) + mt8163_apll1_disable(afe); + else + mt8163_apll2_disable(afe); + break; + default: + break; + } + + return 0; +} + +static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + + i2s_priv = get_i2s_priv_by_name(afe, w->name); + + if (!i2s_priv) + return -EINVAL; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + mt8163_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate); + break; + case SND_SOC_DAPM_POST_PMD: + i2s_priv->mclk_rate = 0; + mt8163_mck_disable(afe, i2s_priv->mclk_id); + break; + default: + break; + } + + return 0; +} + +static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = { + SND_SOC_DAPM_MIXER("I2S1_CH1", SND_SOC_NOPM, 0, 0, + mtk_i2s1_ch1_mix, + ARRAY_SIZE(mtk_i2s1_ch1_mix)), + SND_SOC_DAPM_MIXER("I2S1_CH2", SND_SOC_NOPM, 0, 0, + mtk_i2s1_ch2_mix, + ARRAY_SIZE(mtk_i2s1_ch2_mix)), + + SND_SOC_DAPM_MIXER("I2S3_CH1", SND_SOC_NOPM, 0, 0, + mtk_i2s3_ch1_mix, + ARRAY_SIZE(mtk_i2s3_ch1_mix)), + SND_SOC_DAPM_MIXER("I2S3_CH2", SND_SOC_NOPM, 0, 0, + mtk_i2s3_ch2_mix, + ARRAY_SIZE(mtk_i2s3_ch2_mix)), + + /* i2s en*/ + SND_SOC_DAPM_SUPPLY_S("I2S0_EN", SUPPLY_SEQ_I2S_EN, + AFE_I2S_CON, AFE_I2S_S_I2S_EN_SHIFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2S1_EN", SUPPLY_SEQ_I2S_EN, + AFE_I2S_CON1, AFE_I2S_M_I2S_EN_SHIFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2S2_EN", SUPPLY_SEQ_I2S_EN, + AFE_I2S_CON2, AFE_I2S_S_I2S_EN_SHIFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S("I2S3_EN", SUPPLY_SEQ_I2S_EN, + AFE_I2S_CON3, AFE_I2S_M_I2S_EN_SHIFT, 0, + NULL, 0), + + /* i2s hd en */ + SND_SOC_DAPM_SUPPLY_S(I2S0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + AFE_I2S_CON, AFE_I2S_S_I2S_HD_EN_SHIFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S(I2S1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + AFE_I2S_CON1, AFE_I2S_M_I2S_HD_EN_SHIFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S(I2S2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + AFE_I2S_CON2, AFE_I2S_S_I2S_HD_EN_SHIFT, 0, + NULL, 0), + SND_SOC_DAPM_SUPPLY_S(I2S3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, + AFE_I2S_CON3, AFE_I2S_M_I2S_HD_EN_SHIFT, 0, + NULL, 0), + + /* i2s mclk en */ + SND_SOC_DAPM_SUPPLY_S(I2S0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2S1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2S2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(I2S3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, + SND_SOC_NOPM, 0, 0, + mtk_mclk_en_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + /* apll */ + SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL, + SND_SOC_NOPM, 0, 0, + mtk_apll_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL, + SND_SOC_NOPM, 0, 0, + mtk_apll_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), +}; + +static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + + i2s_priv = get_i2s_priv_by_name(afe, sink->name); + + if (!i2s_priv) + return 0; + + if (i2s_priv->share_i2s_id < 0) + return 0; + + return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name); +} + +static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + + i2s_priv = get_i2s_priv_by_name(afe, sink->name); + + if (!i2s_priv) + return 0; + + if (get_i2s_id_by_name(afe, sink->name) == + get_i2s_id_by_name(afe, source->name)) + return i2s_priv->low_jitter_en; + + /* check if share i2s need hd en */ + if (i2s_priv->share_i2s_id < 0) + return 0; + + if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) + return i2s_priv->low_jitter_en; + + return 0; +} + +static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + int cur_apll; + int i2s_need_apll; + + i2s_priv = get_i2s_priv_by_name(afe, w->name); + + if (!i2s_priv) + return 0; + + /* which apll */ + cur_apll = mt8163_get_apll_by_name(source->name); + + /* choose APLL from i2s rate */ + i2s_need_apll = mt8163_get_apll_by_rate(i2s_priv->rate); + + return (i2s_need_apll == cur_apll) ? 1 : 0; +} + +static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + + i2s_priv = get_i2s_priv_by_name(afe, sink->name); + + if (!i2s_priv) + return 0; + + if (get_i2s_id_by_name(afe, sink->name) == + get_i2s_id_by_name(afe, source->name)) + return (i2s_priv->mclk_rate > 0) ? 1 : 0; + + /* check if share i2s need mclk */ + if (i2s_priv->share_i2s_id < 0) + return 0; + + if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) + return (i2s_priv->mclk_rate > 0) ? 1 : 0; + + return 0; +} + +static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_dapm_widget *w = sink; + struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); + struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); + struct mtk_afe_i2s_priv *i2s_priv; + int cur_apll; + + i2s_priv = get_i2s_priv_by_name(afe, w->name); + + if (!i2s_priv) + return 0; + + /* which apll */ + cur_apll = mt8163_get_apll_by_name(source->name); + + return (i2s_priv->mclk_apll == cur_apll) ? 1 : 0; +} + +static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = { + /* i2s0 */ + {"I2S0", NULL, "I2S0_EN"}, + {"I2S0", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, + {"I2S0", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, + {"I2S0", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, + + {"I2S0", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S0", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S0", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S0", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2S0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2S0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2S0", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S0", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S0", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S0", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2S0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2S0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2s1 */ + {"I2S1_CH1", "DL1_CH1", "DL1"}, + {"I2S1_CH2", "DL1_CH2", "DL1"}, + + {"I2S1_CH1", "DL2_CH1", "DL2"}, + {"I2S1_CH2", "DL2_CH2", "DL2"}, + + {"I2S1", NULL, "I2S1_CH1"}, + {"I2S1", NULL, "I2S1_CH2"}, + + {"I2S1", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, + {"I2S1", NULL, "I2S1_EN"}, + {"I2S1", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, + {"I2S1", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, + + {"I2S1", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S1", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S1", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S1", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2S1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2S1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2S1", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S1", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S1", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S1", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2S1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2S1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2s2 */ + {"I2S2", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, + {"I2S2", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, + {"I2S2", NULL, "I2S2_EN"}, + {"I2S2", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, + + {"I2S2", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S2", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S2", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S2", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2S2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2S2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2S2", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S2", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S2", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S2", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2S2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2S2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, + + /* i2s3 */ + {"I2S3_CH1", "DL1_CH1", "DL1"}, + {"I2S3_CH2", "DL1_CH2", "DL1"}, + + {"I2S3_CH1", "DL2_CH1", "DL2"}, + {"I2S3_CH2", "DL2_CH2", "DL2"}, + + {"I2S3", NULL, "I2S3_CH1"}, + {"I2S3", NULL, "I2S3_CH2"}, + + {"I2S3", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, + {"I2S3", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, + {"I2S3", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, + {"I2S3", NULL, "I2S3_EN"}, + + {"I2S3", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S3", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S3", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {"I2S3", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, + {I2S3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, + {I2S3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, + + {"I2S3", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S3", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S3", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {"I2S3", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, + {I2S3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, + {I2S3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, +}; + +/* dai ops */ +static int mtk_i2s_master_config(struct mtk_base_afe *afe, + int i2s_id, struct snd_pcm_hw_params *params) +{ + struct mt8163_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id]; + snd_pcm_format_t format = params_format(params); + unsigned int i2s_wlen = get_i2s_wlen(format); + unsigned int rate = params_rate(params); + unsigned int rate_val = mt8163_general_rate_transform(rate); + int ret; + u32 val = 0, mask = 0; + + if (rate_val < 0) + return rate_val; + + mask |= AFE_I2S_M_I2S_WLEN; + val |= FIELD_PREP(AFE_I2S_M_I2S_WLEN, i2s_wlen); + + mask |= AFE_I2S_M_I2S_FMT; + val |= FIELD_PREP(AFE_I2S_M_I2S_FMT, i2s_priv->use_i2s); + + mask |= AFE_I2S_M_INV_LRCK; + + mask |= AFE_I2S_M_I2S_OUT_MODE; + val |= FIELD_PREP(AFE_I2S_M_I2S_OUT_MODE, rate_val); + + mask |= AFE_I2S_M_I2S_LR_SWAP; + + ret = regmap_update_bits(afe->regmap, i2s_priv->con_reg, mask, val); + if (ret) + return ret; + + /* configure format of I2S output ports */ + if (i2s_priv->output_fmt_bits) { + if (i2s_wlen == I2S_WLEN_32_BIT) + ret = regmap_set_bits(afe->regmap, AFE_CONN_24BIT, + i2s_priv->output_fmt_bits); + else + ret = regmap_clear_bits(afe->regmap, AFE_CONN_24BIT, + i2s_priv->output_fmt_bits); + + if (ret) + return ret; + } + + i2s_priv->rate = rate; + return 0; +} + +static int mtk_i2s_slave_config(struct mtk_base_afe *afe, + int i2s_id, struct snd_pcm_hw_params *params) +{ + struct mt8163_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id]; + unsigned int rate = params_rate(params); + snd_pcm_format_t format = params_format(params); + int ret; + u32 val = 0, mask = 0; + + mask |= AFE_I2S_S_I2S_WLEN; + val |= FIELD_PREP(AFE_I2S_S_I2S_WLEN, get_i2s_wlen(format)); + + mask |= AFE_I2S_S_I2S_FMT; + val |= FIELD_PREP(AFE_I2S_S_I2S_FMT, i2s_priv->use_i2s); + + mask |= AFE_I2S_S_INV_LRCK; + mask |= AFE_I2S_S_INV_PAD_CTRL; + mask |= AFE_I2S_S_I2S_LOOPBACK; + + mask |= AFE_I2S_S_I2SIN_PAD_SEL; + val |= FIELD_PREP(AFE_I2S_S_I2SIN_PAD_SEL, I2S_IN_PAD_IO_MUX); + + mask |= AFE_I2S_S_BCK_INV; + mask |= AFE_I2S_S_BCK_NEG_EG_LATCH; + mask |= AFE_I2S_S_PHASE_SHIFT_FIX; + + ret = regmap_update_bits(afe->regmap, i2s_priv->con_reg, mask, val); + if (ret) + return ret; + + i2s_priv->rate = rate; + return 0; +} + +static int mtk_dai_i2s_config(struct mtk_base_afe *afe, + struct snd_pcm_hw_params *params, + int i2s_id) +{ + struct mt8163_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id]; + int ret; + + if (!i2s_priv) + return -EINVAL; + + switch (i2s_id) { + case MT8163_AFE_DAI_I2S0: + case MT8163_AFE_DAI_I2S2: + ret = mtk_i2s_slave_config(afe, i2s_id, params); + break; + case MT8163_AFE_DAI_I2S1: + case MT8163_AFE_DAI_I2S3: + ret = mtk_i2s_master_config(afe, i2s_id, params); + break; + default: + return -EINVAL; + } + + if (ret) + return ret; + + /* set share i2s */ + if (i2s_priv->share_i2s_id >= 0) + ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id); + + return ret; +} + +static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + + return mtk_dai_i2s_config(afe, params, dai->id); +} + +static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct mtk_base_afe *afe = dev_get_drvdata(dai->dev); + struct mt8163_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[dai->id]; + int apll; + int apll_rate; + + if (!i2s_priv) { + dev_err(afe->dev, "Invalid I2S private data\n"); + return -EINVAL; + } + + if (dir != SND_SOC_CLOCK_OUT) { + dev_err(afe->dev, "Invalid clock direction\n"); + return -EINVAL; + } + + apll = mt8163_get_apll_by_rate(freq); + apll_rate = mt8163_get_apll_rate(apll); + + if (freq > apll_rate) { + dev_err(afe->dev, "freq > apll_rate freq=%d apll_rate=%d\n", freq, apll_rate); + return -EINVAL; + } + + if (apll_rate % freq != 0) { + dev_err(afe->dev, "apll_rate mod freq != 0 freq=%d apll_rate=%d\n", freq, apll_rate); + return -EINVAL; + } + + i2s_priv->mclk_rate = freq; + i2s_priv->mclk_apll = apll; + + if (i2s_priv->share_i2s_id > 0) { + struct mtk_afe_i2s_priv *share_i2s_priv; + + share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id]; + if (!share_i2s_priv) + return -EINVAL; + + + share_i2s_priv->mclk_rate = i2s_priv->mclk_rate; + share_i2s_priv->mclk_apll = i2s_priv->mclk_apll; + } + + return 0; +} + +static int mtk_dai_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); + struct mt8163_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2s_priv; + + switch (dai->id) { + case MT8163_AFE_DAI_I2S0: + case MT8163_AFE_DAI_I2S1: + case MT8163_AFE_DAI_I2S2: + case MT8163_AFE_DAI_I2S3: + break; + default: + return -EINVAL; + } + i2s_priv = afe_priv->dai_priv[dai->id]; + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_LEFT_J: + i2s_priv->use_i2s = false; + break; + case SND_SOC_DAIFMT_I2S: + i2s_priv->use_i2s = true; + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct snd_soc_dai_ops mtk_dai_i2s_ops = { + .hw_params = mtk_dai_i2s_hw_params, + .set_sysclk = mtk_dai_i2s_set_sysclk, + .set_fmt = mtk_dai_i2s_set_fmt, +}; + +/* dai driver */ +#define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\ + SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_176400 |\ + SNDRV_PCM_RATE_192000) + +#define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = { + { + .name = "I2S0", + .id = MT8163_AFE_DAI_I2S0, + .capture = { + .stream_name = "I2S0", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_I2S_RATES, + .formats = MTK_I2S_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2S1", + .id = MT8163_AFE_DAI_I2S1, + .playback = { + .stream_name = "I2S1", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_I2S_RATES, + .formats = MTK_I2S_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2S2", + .id = MT8163_AFE_DAI_I2S2, + .capture = { + .stream_name = "I2S2", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_I2S_RATES, + .formats = MTK_I2S_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, + { + .name = "I2S3", + .id = MT8163_AFE_DAI_I2S3, + .playback = { + .stream_name = "I2S3", + .channels_min = 1, + .channels_max = 2, + .rates = MTK_I2S_RATES, + .formats = MTK_I2S_FORMATS, + }, + .ops = &mtk_dai_i2s_ops, + }, +}; + +/* this enum is merely for mtk_afe_i2s_priv declare */ +enum { + DAI_I2S0 = 0, + DAI_I2S1, + DAI_I2S2, + DAI_I2S3, + DAI_I2S_NUM, +}; + +static const struct mtk_afe_i2s_priv mt8163_i2s_priv[DAI_I2S_NUM] = { + [DAI_I2S0] = { + .id = MT8163_AFE_DAI_I2S0, + .mclk_id = MT8163_I2S0_MCK, + .share_i2s_id = -1, + .con_reg = AFE_I2S_CON, + .output_fmt_bits = 0, + }, + [DAI_I2S1] = { + .id = MT8163_AFE_DAI_I2S1, + .mclk_id = MT8163_I2S1_MCK, + .share_i2s_id = -1, + .con_reg = AFE_I2S_CON1, + .output_fmt_bits = GENMASK(4, 3), /* O03 - O04 */ + }, + [DAI_I2S2] = { + .id = MT8163_AFE_DAI_I2S2, + .mclk_id = MT8163_I2S2_MCK, + .share_i2s_id = -1, + .con_reg = AFE_I2S_CON2, + .output_fmt_bits = 0, + }, + [DAI_I2S3] = { + .id = MT8163_AFE_DAI_I2S3, + .mclk_id = MT8163_I2S3_MCK, + .share_i2s_id = -1, + .con_reg = AFE_I2S_CON3, + .output_fmt_bits = GENMASK(1, 0), /* O00 - O01 */ + }, +}; + +/** + * mt8163_dai_i2s_set_share() - Set up I2S ports to share a single clock. + * @afe: Pointer to &struct mtk_base_afe + * @main_i2s_name: The name of the I2S port that will provide the clock + * @secondary_i2s_name: The name of the I2S port that will use this clock + */ +int mt8163_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name, + const char *secondary_i2s_name) +{ + struct mtk_afe_i2s_priv *secondary_i2s_priv; + int main_i2s_id; + + secondary_i2s_priv = get_i2s_priv_by_name(afe, secondary_i2s_name); + if (!secondary_i2s_priv) + return -EINVAL; + + main_i2s_id = get_i2s_id_by_name(afe, main_i2s_name); + if (main_i2s_id < 0) + return main_i2s_id; + + secondary_i2s_priv->share_i2s_id = main_i2s_id; + + return 0; +} +EXPORT_SYMBOL_GPL(mt8163_dai_i2s_set_share); + +static int mt8163_dai_i2s_set_priv(struct mtk_base_afe *afe) +{ + struct mt8163_afe_private *afe_priv = afe->platform_priv; + struct mtk_afe_i2s_priv *i2s_priv; + int i; + + for (i = 0; i < DAI_I2S_NUM; i++) { + i2s_priv = devm_kzalloc(afe->dev, + sizeof(struct mtk_afe_i2s_priv), + GFP_KERNEL); + if (!i2s_priv) + return -ENOMEM; + + memcpy(i2s_priv, &mt8163_i2s_priv[i], + sizeof(struct mtk_afe_i2s_priv)); + + afe_priv->dai_priv[mt8163_i2s_priv[i].id] = i2s_priv; + } + + return 0; +} + +int mt8163_dai_i2s_register(struct mtk_base_afe *afe) +{ + struct mtk_base_afe_dai *dai; + + dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); + if (!dai) + return -ENOMEM; + + list_add(&dai->list, &afe->sub_dais); + + dai->dai_drivers = mtk_dai_i2s_driver; + dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver); + + dai->controls = mtk_dai_i2s_controls; + dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls); + dai->dapm_widgets = mtk_dai_i2s_widgets; + dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets); + dai->dapm_routes = mtk_dai_i2s_routes; + dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes); + + /* set all dai i2s private data */ + return mt8163_dai_i2s_set_priv(afe); +} From bc7c588008ade6d3a4565ff178f47ff95de6cfd7 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Mon, 9 Feb 2026 16:55:42 +0000 Subject: [PATCH 064/126] arm64: dts: mediatek: mt8163: Add AFE Add a device node for the AFE (Audio Front End) hardware on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 53 ++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 4e4c2e1958a09c..b8ee4d50bcaae3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -663,6 +663,59 @@ compatible = "mediatek,mt8163-audsys", "syscon"; reg = <0 0x11220000 0 0x1000>; #clock-cells = <1>; + + afe: audio-controller { + compatible = "mediatek,mt8163-afe-pcm"; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_AUDIO>; + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_AUD_2_SEL>, + <&apmixedsys CLK_APMIXED_AUD1PLL>, + <&audiosys CLK_AUDIO_APLL_TUNER>, + <&audiosys CLK_AUDIO_APLL1_DIV0>, + <&apmixedsys CLK_APMIXED_AUD2PLL>, + <&audiosys CLK_AUDIO_APLL2_TUNER>, + <&audiosys CLK_AUDIO_APLL2_DIV0>, + <&audiosys CLK_AUDIO_AFE>, + <&audiosys CLK_AUDIO_ADC>, + <&audiosys CLK_AUDIO_DAC>, + <&audiosys CLK_AUDIO_DAC_PREDIS>, + <&audiosys CLK_AUDIO_22M>, + <&audiosys CLK_AUDIO_24M>, + <&audiosys CLK_AUDIO_I2S>, + <&audiosys CLK_AUDIO_APLL_I2S0>, + <&audiosys CLK_AUDIO_APLL_I2S1>, + <&audiosys CLK_AUDIO_APLL_I2S2>, + <&audiosys CLK_AUDIO_APLL_I2S3>, + <&clk26m>; + clock-names = "infrasys_aud", + "top_pdn_aud", + "top_pdn_aud_bus", + "aud_1_sel", + "aud_2_sel", + "apll1", + "apll1_tuner", + "apll1_div", + "apll2", + "apll2_tuner", + "apll2_div", + "afe", + "adc", + "dac", + "dac_predis", + "22m", + "24m", + "top_i2s", + "i2s0", + "i2s1", + "i2s2", + "i2s3", + "clk26m"; + status = "disabled"; + }; }; mmc0: mmc@11230000 { From 481d079b0f9411e07d9910e52098a15bfdc75c51 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sat, 13 Dec 2025 21:39:02 +0000 Subject: [PATCH 065/126] dt-bindings: mailbox: Add bindings for MT8163 GCE Add device tree bindings for the GCE mailbox on the MT8163 SoC. Signed-off-by: bengris32 --- .../mailbox/mediatek,gce-mailbox.yaml | 4 +- include/dt-bindings/gce/mediatek,mt8163-gce.h | 127 ++++++++++++++++++ 2 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/gce/mediatek,mt8163-gce.h diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml index 587126d03fc651..a47f417ca9cf62 100644 --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml @@ -27,7 +27,9 @@ properties: - mediatek,mt8195-gce - mediatek,mt8196-gce - items: - - const: mediatek,mt6795-gce + - enum: + - mediatek,mt6795-gce + - mediatek,mt8163-gce - const: mediatek,mt8173-gce "#mbox-cells": diff --git a/include/dt-bindings/gce/mediatek,mt8163-gce.h b/include/dt-bindings/gce/mediatek,mt8163-gce.h new file mode 100644 index 00000000000000..8c5a378174d7f7 --- /dev/null +++ b/include/dt-bindings/gce/mediatek,mt8163-gce.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#ifndef _DT_BINDINGS_GCE_MT8163_H +#define _DT_BINDINGS_GCE_MT8163_H + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_NORMAL 1 +#define CMDQ_THR_PRIO_NORMAL_2 2 +#define CMDQ_THR_PRIO_MEDIUM 3 +#define CMDQ_THR_PRIO_MEDIUM_2 4 +#define CMDQ_THR_PRIO_HIGH 5 +#define CMDQ_THR_PRIO_HIGHER 6 +#define CMDQ_THR_PRIO_HIGHEST 7 + +/* GCE SUBSYS */ +#define SUBSYS_1300XXXX 0 +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 +#define SUBSYS_1500XXXX 4 +#define SUBSYS_1600XXXX 5 +#define SUBSYS_1700XXXX 6 +#define SUBSYS_1800XXXX 7 +#define SUBSYS_1000XXXX 8 +#define SUBSYS_1001XXXX 9 +#define SUBSYS_1002XXXX 10 +#define SUBSYS_1003XXXX 11 +#define SUBSYS_1004XXXX 12 +#define SUBSYS_1005XXXX 13 +#define SUBSYS_1020XXXX 14 +#define SUBSYS_1021XXXX 15 +#define SUBSYS_1120XXXX 16 +#define SUBSYS_1121XXXX 17 +#define SUBSYS_1122XXXX 18 +#define SUBSYS_1123XXXX 19 +#define SUBSYS_1124XXXX 20 +#define SUBSYS_1125XXXX 21 +#define SUBSYS_1126XXXX 22 + +/* GCE HW EVENT */ +#define CMDQ_EVENT_MDP_RDMA0_SOF 0 +#define CMDQ_EVENT_MDP_RSZ0_SOF 1 +#define CMDQ_EVENT_MDP_RSZ1_SOF 2 +#define CMDQ_EVENT_MDP_TDSHP_SOF 3 +#define CMDQ_EVENT_MDP_WDMA_SOF 4 +#define CMDQ_EVENT_MDP_WROT_SOF 5 +#define CMDQ_EVENT_DISP_OVL0_SOF 6 +#define CMDQ_EVENT_DISP_OVL1_SOF 7 +#define CMDQ_EVENT_DISP_RDMA0_SOF 8 +#define CMDQ_EVENT_DISP_RDMA1_SOF 9 +#define CMDQ_EVENT_DISP_WDMA0_SOF 10 +#define CMDQ_EVENT_DISP_COLOR_SOF 11 +#define CMDQ_EVENT_DISP_CCORR_SOF 12 +#define CMDQ_EVENT_DISP_AAL_SOF 13 +#define CMDQ_EVENT_DISP_GAMMA_SOF 14 +#define CMDQ_EVENT_DISP_DITHER_SOF 15 +#define CMDQ_EVENT_DISP_UFOE_SOF 16 +#define CMDQ_EVENT_DISP_PWM0_SOF 17 +#define CMDQ_EVENT_DISP_WDMA1_SOF 18 +#define CMDQ_EVENT_UFOD_RDMA0_L0_SOF 19 +#define CMDQ_EVENT_UFOD_RDMA0_L1_SOF 20 +#define CMDQ_EVENT_UFOD_RDMA0_L2_SOF 21 +#define CMDQ_EVENT_UFOD_RDMA0_L3_SOF 22 +#define CMDQ_EVENT_UFOD_RDMA1_L0_SOF 23 +#define CMDQ_EVENT_UFOD_RDMA1_L1_SOF 24 +#define CMDQ_EVENT_UFOD_RDMA1_L2_SOF 25 +#define CMDQ_EVENT_UFOD_RDMA1_L3_SOF 26 +#define CMDQ_EVENT_DISP_DSC_SOF 27 +#define CMDQ_EVENT_MDP_RDMA0_EOF 28 +#define CMDQ_EVENT_MDP_RSZ0_EOF 29 +#define CMDQ_EVENT_MDP_RSZ1_EOF 30 +#define CMDQ_EVENT_MDP_TDSHP_EOF 31 +#define CMDQ_EVENT_MDP_WDMA_EOF 32 +#define CMDQ_EVENT_MDP_WROT_WRITE_EOF 33 +#define CMDQ_EVENT_MDP_WROT_READ_EOF 34 +#define CMDQ_EVENT_DISP_OVL0_EOF 35 +#define CMDQ_EVENT_DISP_OVL1_EOF 36 +#define CMDQ_EVENT_DISP_RDMA0_EOF 37 +#define CMDQ_EVENT_DISP_RDMA1_EOF 38 +#define CMDQ_EVENT_DISP_WDMA0_EOF 39 +#define CMDQ_EVENT_DISP_COLOR_EOF 40 +#define CMDQ_EVENT_DISP_CCORR_EOF 41 +#define CMDQ_EVENT_DISP_AAL_EOF 42 +#define CMDQ_EVENT_DISP_GAMMA_EOF 43 +#define CMDQ_EVENT_DISP_DITHER_EOF 44 +#define CMDQ_EVENT_DISP_UFOE_EOF 45 +#define CMDQ_EVENT_DISP_DPI0_EOF 46 +#define CMDQ_EVENT_DISP_WDMA1_EOF 47 +#define CMDQ_EVENT_UFOD_RDMA0_L0_EOF 48 +#define CMDQ_EVENT_UFOD_RDMA0_L1_EOF 49 +#define CMDQ_EVENT_UFOD_RDMA0_L2_EOF 50 +#define CMDQ_EVENT_UFOD_RDMA0_L3_EOF 51 +#define CMDQ_EVENT_UFOD_RDMA1_L0_EOF 52 +#define CMDQ_EVENT_UFOD_RDMA1_L1_EOF 53 +#define CMDQ_EVENT_UFOD_RDMA1_L2_EOF 54 +#define CMDQ_EVENT_UFOD_RDMA1_L3_EOF 55 +#define CMDQ_EVENT_DISP_DPI1_EOF 56 +#define CMDQ_EVENT_DISP_DSC_EOF 57 +#define CMDQ_EVENT_MUTEX0_STREAM_EOF 58 +#define CMDQ_EVENT_MUTEX1_STREAM_EOF 59 +#define CMDQ_EVENT_MUTEX2_STREAM_EOF 60 +#define CMDQ_EVENT_MUTEX3_STREAM_EOF 61 +#define CMDQ_EVENT_MUTEX4_STREAM_EOF 62 +#define CMDQ_EVENT_MUTEX5_STREAM_EOF 63 +#define CMDQ_EVENT_MUTEX6_STREAM_EOF 64 +#define CMDQ_EVENT_MUTEX7_STREAM_EOF 65 +#define CMDQ_EVENT_MUTEX8_STREAM_EOF 66 +#define CMDQ_EVENT_MUTEX9_STREAM_EOF 67 +#define CMDQ_EVENT_BUF_UNDERRUN_EVENT_0 68 +#define CMDQ_EVENT_BUF_UNDERRUN_EVENT_1 69 +#define CMDQ_EVENT_DSI0_TE_EVENT 70 +#define CMDQ_EVENT_ISP_B_EOF 130 +#define CMDQ_EVENT_ISP_A_EOF 131 +#define CMDQ_EVENT_ISP_P2_0_EOF 131 +#define CMDQ_EVENT_ISP_P2_1_EOF 130 +#define CMDQ_EVENT_SENINF_1_FIFO_FULL 135 +#define CMDQ_EVENT_VENC_DONE 257 +#define CMDQ_EVENT_JPGENC_DONE 258 +#define CMDQ_EVENT_JPGDEC_DONE 259 +#define CMDQ_EVENT_VENC_MB_DONE 260 +#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 261 + +#endif From fe3716452597eb1713cbb9dd3bf64034db1ae26d Mon Sep 17 00:00:00 2001 From: bengris32 Date: Mon, 1 Sep 2025 01:37:25 +0100 Subject: [PATCH 066/126] arm64: dts: mediatek: mt8163: Add GCE Add device tree node for the GCE mailbox on the MT8163 SoC. Signed-off-by: bengris32 --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index b8ee4d50bcaae3..c6fde272d1d0db 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -432,6 +433,15 @@ clock-names = "rng"; }; + gce: mailbox@10212000 { + compatible = "mediatek,mt8163-gce", "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + #mbox-cells = <2>; + }; + gic: interrupt-controller@10221000 { compatible = "arm,gic-400"; reg = <0 0x10221000 0 0x1000>, From 7500ebc9a49c9c6092e166e1afdb98459a11d122 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Mon, 1 Sep 2025 00:34:29 +0100 Subject: [PATCH 067/126] dt-bindings: mtk-mmsys: Add bindings for MT8163 MMSYS Add device tree bindings for the Multi Media System (MMSYS) on the MT8163 SoC. Signed-off-by: bengris32 --- .../bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + .../dt-bindings/clock/mediatek,mt8163-mmsys.h | 55 +++++++++++++++++++ .../dt-bindings/reset/mediatek,mt8163-mmsys.h | 41 ++++++++++++++ 3 files changed, 97 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt8163-mmsys.h create mode 100644 include/dt-bindings/reset/mediatek,mt8163-mmsys.h diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 3f4262e93c789c..acad94fe06ca9c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt6779-mmsys - mediatek,mt6795-mmsys - mediatek,mt6797-mmsys + - mediatek,mt8163-mmsys - mediatek,mt8167-mmsys - mediatek,mt8173-mmsys - mediatek,mt8183-mmsys diff --git a/include/dt-bindings/clock/mediatek,mt8163-mmsys.h b/include/dt-bindings/clock/mediatek,mt8163-mmsys.h new file mode 100644 index 00000000000000..06280806d55038 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8163-mmsys.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_MT8163_MMSYS_H +#define _DT_BINDINGS_CLOCK_MT8163_MMSYS_H + +#define CLK_MM_SMI_COMMON 0 +#define CLK_MM_SMI_LARB0 1 +#define CLK_MM_CAM_MDP 2 +#define CLK_MM_MDP_RDMA 3 +#define CLK_MM_MDP_RSZ0 4 +#define CLK_MM_MDP_RSZ1 5 +#define CLK_MM_MDP_TDSHP 6 +#define CLK_MM_MDP_WDMA 7 +#define CLK_MM_MDP_WROT 8 +#define CLK_MM_FAKE_ENG 9 +#define CLK_MM_DISP_OVL0 10 +#define CLK_MM_DISP_OVL1 11 +#define CLK_MM_DISP_RDMA0 12 +#define CLK_MM_DISP_RDMA1 13 +#define CLK_MM_DISP_WDMA0 14 +#define CLK_MM_DISP_COLOR 15 +#define CLK_MM_DISP_CCORR 16 +#define CLK_MM_DISP_AAL 17 +#define CLK_MM_DISP_GAMMA 18 +#define CLK_MM_DISP_DITHER 19 +#define CLK_MM_DISP_UFOE 20 +#define CLK_MM_LARB4_AXI_ASIF_MM 21 +#define CLK_MM_LARB4_AXI_ASIF_MJC 22 +#define CLK_MM_DISP_WDMA1 23 +#define CLK_MM_UFOD_RDMA0_L0 24 +#define CLK_MM_UFOD_RDMA0_L1 25 +#define CLK_MM_UFOD_RDMA0_L2 26 +#define CLK_MM_UFOD_RDMA0_L3 27 +#define CLK_MM_UFOD_RDMA1_L0 28 +#define CLK_MM_UFOD_RDMA1_L1 29 +#define CLK_MM_UFOD_RDMA1_L2 30 +#define CLK_MM_UFOD_RDMA1_L3 31 +#define CLK_MM_DISP_PWM_MM 32 +#define CLK_MM_DISP_PWM_26M 33 +#define CLK_MM_DSI_ENGINE 34 +#define CLK_MM_DSI_DIGITAL 35 +#define CLK_MM_DPI0_PIXEL 36 +#define CLK_MM_DPI0_ENGINE 37 +#define CLK_MM_LVDS_PIXEL 38 +#define CLK_MM_LVDS_CTS 39 +#define CLK_MM_DPI1_PIXEL 40 +#define CLK_MM_DPI1_ENGINE 41 +#define CLK_MM_HDMI_PIXEL 42 +#define CLK_MM_HDMI_SPDIF 43 +#define CLK_MM_HDMI_ADSP 44 +#define CLK_MM_HDMI_PLLCK 45 +#define CLK_MM_DISP_DSC_ENGINE 46 +#define CLK_MM_DISP_DSC_MEM 47 + +#endif /* _DT_BINDINGS_CLOCK_MT8163_MMSYS_H */ diff --git a/include/dt-bindings/reset/mediatek,mt8163-mmsys.h b/include/dt-bindings/reset/mediatek,mt8163-mmsys.h new file mode 100644 index 00000000000000..ef0e35e168fbba --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt8163-mmsys.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MEDIATEK_MT8163_MMSYS_H +#define _DT_BINDINGS_RESET_MEDIATEK_MT8163_MMSYS_H + +#define MT8163_MMSYS_RST_SMI_COMMON 0 +#define MT8163_MMSYS_RST_SMI_LARB0 1 +#define MT8163_MMSYS_RST_CAM_MDP 2 +#define MT8163_MMSYS_RST_MDP_RDMA 3 +#define MT8163_MMSYS_RST_MDP_RSZ0 4 +#define MT8163_MMSYS_RST_MDP_RSZ1 5 +#define MT8163_MMSYS_RST_MDP_TDSHP 6 +#define MT8163_MMSYS_RST_MDP_WDMA 7 +#define MT8163_MMSYS_RST_MDP_WROT 8 +#define MT8163_MMSYS_RST_FAKE_ENG 9 +#define MT8163_MMSYS_RST_MUTEX 10 +#define MT8163_MMSYS_RST_DISP_OVL0 11 +#define MT8163_MMSYS_RST_DISP_OVL1 12 +#define MT8163_MMSYS_RST_DISP_RDMA0 13 +#define MT8163_MMSYS_RST_DISP_RDMA1 14 +#define MT8163_MMSYS_RST_DISP_WDMA0 15 +#define MT8163_MMSYS_RST_DISP_COLOR 16 +#define MT8163_MMSYS_RST_DISP_CCORR 17 +#define MT8163_MMSYS_RST_DISP_AAL 18 +#define MT8163_MMSYS_RST_DISP_GAMMA 19 +#define MT8163_MMSYS_RST_DISP_DITHER 20 +#define MT8163_MMSYS_RST_DISP_UFOE 21 +#define MT8163_MMSYS_RST_DISP_PWM 22 +#define MT8163_MMSYS_RST_DSI 23 +#define MT8163_MMSYS_RST_DPI0 24 +#define MT8163_MMSYS_RST_SMI_COMMON_GLB 25 +#define MT8163_MMSYS_RST_SMI_LARB0_GLB 26 +#define MT8163_MMSYS_RST_AXI_ASF 27 +#define MT8163_MMSYS_RST_DISP_WDMA1 28 +#define MT8163_MMSYS_RST_UFOD_RDMA0 29 +#define MT8163_MMSYS_RST_UFOD_RDMA1 30 +#define MT8163_MMSYS_RST_DPI1 31 +#define MT8163_MMSYS_RST_LVDS 32 +#define MT8163_MMSYS_RST_LCM 33 + +#endif /* _DT_BINDINGS_RESET_MEDIATEK_MT8163_MMSYS_H */ From d4dbd58c4e6790fb6674240583e7f026e47de5fb Mon Sep 17 00:00:00 2001 From: bengris32 Date: Mon, 1 Sep 2025 00:36:03 +0100 Subject: [PATCH 068/126] soc: mtk-mmsys: Add support for MT8163 Add support for the Multi Media System (MMSYS) on the MT8163 SoC. Signed-off-by: bengris32 --- drivers/clk/mediatek/Kconfig | 7 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8163-mmsys.c | 109 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 21 +++++ drivers/soc/mediatek/mt8163-mmsys.h | 106 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 13 +++ 6 files changed, 257 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8163-mmsys.c create mode 100644 drivers/soc/mediatek/mt8163-mmsys.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index b5e25124c67fd7..74584270755b5d 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -506,6 +506,13 @@ config COMMON_CLK_MT8163_MFGCFG help This driver supports MediaTek MT8163 mfgcfg clocks. +config COMMON_CLK_MT8163_MMSYS + tristate "Clock driver for MediaTek MT8163 mmsys" + depends on COMMON_CLK_MT8163 + default COMMON_CLK_MT8163 + help + This driver supports MediaTek MT8163 mmsys clocks. + config COMMON_CLK_MT8163_VDECSYS tristate "Clock driver for MediaTek MT8163 vdecsys" depends on COMMON_CLK_MT8163 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 161673c662d1e6..588688012f6dd2 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -77,6 +77,7 @@ obj-$(CONFIG_COMMON_CLK_MT8163) += clk-mt8163-apmixedsys.o clk-mt8163-infracfg.o obj-$(CONFIG_COMMON_CLK_MT8163_AUDSYS) += clk-mt8163-audsys.o obj-$(CONFIG_COMMON_CLK_MT8163_IMGSYS) += clk-mt8163-imgsys.o obj-$(CONFIG_COMMON_CLK_MT8163_MFGCFG) += clk-mt8163-mfgcfg.o +obj-$(CONFIG_COMMON_CLK_MT8163_MMSYS) += clk-mt8163-mmsys.o obj-$(CONFIG_COMMON_CLK_MT8163_VDECSYS) += clk-mt8163-vdecsys.o obj-$(CONFIG_COMMON_CLK_MT8163_VENCSYS) += clk-mt8163-vencsys.o obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167-apmixedsys.o clk-mt8167.o diff --git a/drivers/clk/mediatek/clk-mt8163-mmsys.c b/drivers/clk/mediatek/clk-mt8163-mmsys.c new file mode 100644 index 00000000000000..f2773e8ac4024f --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8163-mmsys.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Ben Grisdale + */ + +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs mm0_cg_regs = { + .set_ofs = 0x0104, + .clr_ofs = 0x0108, + .sta_ofs = 0x0100, +}; + +static const struct mtk_gate_regs mm1_cg_regs = { + .set_ofs = 0x0114, + .clr_ofs = 0x0118, + .sta_ofs = 0x0110, +}; + +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate mm_clks[] = { + /* MM0 */ + GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), + GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), + GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2), + GATE_MM0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "mm_sel", 3), + GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 4), + GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 5), + GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 6), + GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 7), + GATE_MM0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "mm_sel", 8), + GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 9), + GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 10), + GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 11), + GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 12), + GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 13), + GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "rtc_sel", 14), + GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 15), + GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 16), + GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 17), + GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 18), + GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 19), + GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 20), + GATE_MM0(CLK_MM_LARB4_AXI_ASIF_MM, "mm_larb4_mm", "mm_sel", 21), + GATE_MM0(CLK_MM_LARB4_AXI_ASIF_MJC, "mm_larb4_mjc", "mm_sel", 22), + GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 23), + GATE_MM0(CLK_MM_UFOD_RDMA0_L0, "mm_ufodrdma0_l0", "mm_sel", 24), + GATE_MM0(CLK_MM_UFOD_RDMA0_L1, "mm_ufodrdma0_l1", "mm_sel", 25), + GATE_MM0(CLK_MM_UFOD_RDMA0_L2, "mm_ufodrdma0_l2", "mm_sel", 26), + GATE_MM0(CLK_MM_UFOD_RDMA0_L3, "mm_ufodrdma0_l3", "mm_sel", 27), + GATE_MM0(CLK_MM_UFOD_RDMA1_L0, "mm_ufodrdma1_l0", "mm_sel", 28), + GATE_MM0(CLK_MM_UFOD_RDMA1_L1, "mm_ufodrdma1_l1", "mm_sel", 29), + GATE_MM0(CLK_MM_UFOD_RDMA1_L2, "mm_ufodrdma1_l2", "mm_sel", 30), + GATE_MM0(CLK_MM_UFOD_RDMA1_L3, "mm_ufodrdma1_l3", "mm_sel", 31), + + /* MM1 */ + GATE_MM1(CLK_MM_DISP_PWM_MM, "mm_disp_pwm0mm", "mm_sel", 0), + GATE_MM1(CLK_MM_DISP_PWM_26M, "mm_disp_pwm026m", "clk26m", 1), + GATE_MM1(CLK_MM_DSI_ENGINE, "mm_dsi0_engine", "mm_sel", 2), + GATE_MM1(CLK_MM_DSI_DIGITAL, "mm_dsi0_digital", "dsi0_lntc_dsick", 3), + GATE_MM1(CLK_MM_DPI0_PIXEL, "mm_dpi_pixel", "mm_sel", 4), + GATE_MM1(CLK_MM_DPI0_ENGINE, "mm_dpi_engine", "dpi0_sel", 5), + GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "dpi0_sel", 6), + GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx_dig_cts", 7), + GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "mm_sel", 8), + GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "dpi1_sel", 9), + GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 10), + GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2_div1", 11), + GATE_MM1(CLK_MM_HDMI_ADSP, "mm_hdmi_audio", "apll2_div0", 12), + GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13), + GATE_MM1(CLK_MM_DISP_DSC_ENGINE, "mm_disp_dsc_eng", "mm_sel", 14), + GATE_MM1(CLK_MM_DISP_DSC_MEM, "mm_disp_dsc_mem", "mm_sel", 15), +}; + +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; + +static const struct platform_device_id clk_mt8163_mm_id_table[] = { + { .name = "clk-mt8163-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8163_mm_id_table); + +static struct platform_driver clk_mt8163_mm_drv = { + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, + .driver = { + .name = "clk-mt8163-mmsys", + }, + .id_table = clk_mt8163_mm_id_table, +}; +module_platform_driver(clk_mt8163_mm_drv); + +MODULE_AUTHOR("Ben Grisdale "); +MODULE_DESCRIPTION("MediaTek MT8163 mmsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index c86a3f54f35bcc..5060edd7f32d54 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -111,6 +111,19 @@ static const unsigned int mt2712_mtk_ddp_third[] = { DDP_COMPONENT_PWM2, }; +static unsigned int mt8163_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_UFOE, + DDP_COMPONENT_DSI0, + DDP_COMPONENT_PWM0, +}; + static unsigned int mt8167_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, @@ -259,6 +272,12 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .mmsys_dev_num = 1, }; +static const struct mtk_mmsys_driver_data mt8163_mmsys_driver_data = { + .main_path = mt8163_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8163_mtk_ddp_main), + .mmsys_dev_num = 1, +}; + static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { .main_path = mt8167_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), @@ -338,6 +357,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt7623_mmsys_driver_data}, { .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data}, + { .compatible = "mediatek,mt8163-mmsys", + .data = &mt8163_mmsys_driver_data}, { .compatible = "mediatek,mt8167-mmsys", .data = &mt8167_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", diff --git a/drivers/soc/mediatek/mt8163-mmsys.h b/drivers/soc/mediatek/mt8163-mmsys.h new file mode 100644 index 00000000000000..a48509a5accdb4 --- /dev/null +++ b/drivers/soc/mediatek/mt8163-mmsys.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8163_MMSYS_H +#define __SOC_MEDIATEK_MT8163_MMSYS_H + +#include +#include + +#define MT8163_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x030 +#define MT8163_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN 0x038 +#define MT8163_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x03C +#define MT8163_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x058 +#define MT8163_DISP_REG_CONFIG_DISP_UFOE_SEL_IN 0x060 +#define MT8163_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0x064 +#define MT8163_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x06C + +#define MT8163_OVL0_MOUT_EN_MASK GENMASK(1, 0) + +#define MT8163_DITHER_MOUT_EN_RDMA0 0x1 +#define MT8163_DITHER_MOUT_EN_MASK GENMASK(2, 0) + +#define MT8163_UFOE_MOUT_EN_MASK GENMASK(3, 0) + +#define MT8163_RDMA0_SOUT_MASK GENMASK(2, 0) + +#define MT8163_UFOE_SEL_IN_MASK BIT(0) + +#define MT8163_DSI0_SEL_IN_MASK GENMASK(1, 0) + +static const u8 mmsys_mt8163_rst_tb[] = { + /* MMSYS_SW0_RST_B */ + [MT8163_MMSYS_RST_SMI_COMMON] = MMSYS_RST_NR(0, 0), + [MT8163_MMSYS_RST_SMI_LARB0] = MMSYS_RST_NR(0, 1), + [MT8163_MMSYS_RST_CAM_MDP] = MMSYS_RST_NR(0, 2), + [MT8163_MMSYS_RST_MDP_RDMA] = MMSYS_RST_NR(0, 3), + [MT8163_MMSYS_RST_MDP_RSZ0] = MMSYS_RST_NR(0, 4), + [MT8163_MMSYS_RST_MDP_RSZ1] = MMSYS_RST_NR(0, 5), + [MT8163_MMSYS_RST_MDP_TDSHP] = MMSYS_RST_NR(0, 6), + [MT8163_MMSYS_RST_MDP_WDMA] = MMSYS_RST_NR(0, 7), + [MT8163_MMSYS_RST_MDP_WROT] = MMSYS_RST_NR(0, 8), + [MT8163_MMSYS_RST_FAKE_ENG] = MMSYS_RST_NR(0, 9), + [MT8163_MMSYS_RST_MUTEX] = MMSYS_RST_NR(0, 10), + [MT8163_MMSYS_RST_DISP_OVL0] = MMSYS_RST_NR(0, 12), + [MT8163_MMSYS_RST_DISP_OVL1] = MMSYS_RST_NR(0, 13), + [MT8163_MMSYS_RST_DISP_RDMA0] = MMSYS_RST_NR(0, 14), + [MT8163_MMSYS_RST_DISP_RDMA1] = MMSYS_RST_NR(0, 15), + [MT8163_MMSYS_RST_DISP_WDMA0] = MMSYS_RST_NR(0, 16), + [MT8163_MMSYS_RST_DISP_COLOR] = MMSYS_RST_NR(0, 17), + [MT8163_MMSYS_RST_DISP_CCORR] = MMSYS_RST_NR(0, 18), + [MT8163_MMSYS_RST_DISP_AAL] = MMSYS_RST_NR(0, 19), + [MT8163_MMSYS_RST_DISP_GAMMA] = MMSYS_RST_NR(0, 20), + [MT8163_MMSYS_RST_DISP_DITHER] = MMSYS_RST_NR(0, 21), + [MT8163_MMSYS_RST_DISP_UFOE] = MMSYS_RST_NR(0, 22), + [MT8163_MMSYS_RST_DISP_PWM] = MMSYS_RST_NR(0, 23), + [MT8163_MMSYS_RST_DSI] = MMSYS_RST_NR(0, 24), + [MT8163_MMSYS_RST_DPI0] = MMSYS_RST_NR(0, 25), + [MT8163_MMSYS_RST_SMI_COMMON_GLB] = MMSYS_RST_NR(0, 26), + [MT8163_MMSYS_RST_SMI_LARB0_GLB] = MMSYS_RST_NR(0, 27), + [MT8163_MMSYS_RST_AXI_ASF] = MMSYS_RST_NR(0, 28), + [MT8163_MMSYS_RST_DISP_WDMA1] = MMSYS_RST_NR(0, 29), + [MT8163_MMSYS_RST_UFOD_RDMA0] = MMSYS_RST_NR(0, 30), + [MT8163_MMSYS_RST_UFOD_RDMA1] = MMSYS_RST_NR(0, 31), + + /* MMSYS_SW1_RST_B */ + [MT8163_MMSYS_RST_DPI1] = MMSYS_RST_NR(1, 0), + [MT8163_MMSYS_RST_LVDS] = MMSYS_RST_NR(1, 1), + + /* MMSYS_LCM_RST_B */ + [MT8163_MMSYS_RST_LCM] = MMSYS_RST_NR(2, 0), +}; + +/* + * Minimal routing table with one route implemented: + * OVL0 -> COLOR0 -> CCORR -> AAL -> GAMMA -> DITHER -> RDMA0 -> UFOE -> DSI0 + * + * MT8163 has other routes for driving external displays that are not + * implemented here. + */ +static const struct mtk_mmsys_routes mt8163_mmsys_routing_table[] = { + MMSYS_ROUTE(OVL0, COLOR0, + MT8163_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8163_OVL0_MOUT_EN_MASK, + OVL0_MOUT_EN_COLOR0), + MMSYS_ROUTE(OVL0, COLOR0, + MT8163_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0, + COLOR0_SEL_IN_OVL0), + + MMSYS_ROUTE(DITHER0, RDMA0, + MT8163_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8163_DITHER_MOUT_EN_MASK, + MT8163_DITHER_MOUT_EN_RDMA0), + + MMSYS_ROUTE(RDMA0, UFOE, + MT8163_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8163_RDMA0_SOUT_MASK, + 0 /* Single output to DISP_UFOE */), + MMSYS_ROUTE(RDMA0, UFOE, + MT8163_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8163_UFOE_SEL_IN_MASK, + 0 /* Input from DISP_RDMA0 */), + + MMSYS_ROUTE(UFOE, DSI0, + MT8163_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8163_UFOE_MOUT_EN_MASK, + UFOE_MOUT_EN_DSI0), + MMSYS_ROUTE(UFOE, DSI0, + MT8163_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8163_DSI0_SEL_IN_MASK, + 0 /* Input from DISP_UFOE */), +}; + +#endif /* __SOC_MEDIATEK_MT8163_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index bb4639ca0b8cdc..d495683c90ba06 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -14,6 +14,7 @@ #include #include "mtk-mmsys.h" +#include "mt8163-mmsys.h" #include "mt8167-mmsys.h" #include "mt8173-mmsys.h" #include "mt8183-mmsys.h" @@ -53,10 +54,21 @@ static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", }; +static const struct mtk_mmsys_driver_data mt8163_mmsys_driver_data = { + .clk_driver = "clk-mt8163-mm", + .routes = mt8163_mmsys_routing_table, + .num_routes = ARRAY_SIZE(mt8163_mmsys_routing_table), + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .num_resets = 64, +}; + static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { .clk_driver = "clk-mt8167-mm", .routes = mt8167_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .rst_tb = mmsys_mt8163_rst_tb, + .num_resets = ARRAY_SIZE(mmsys_mt8163_rst_tb), }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { @@ -461,6 +473,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt6779-mmsys", .data = &mt6779_mmsys_driver_data }, { .compatible = "mediatek,mt6795-mmsys", .data = &mt6795_mmsys_driver_data }, { .compatible = "mediatek,mt6797-mmsys", .data = &mt6797_mmsys_driver_data }, + { .compatible = "mediatek,mt8163-mmsys", .data = &mt8163_mmsys_driver_data }, { .compatible = "mediatek,mt8167-mmsys", .data = &mt8167_mmsys_driver_data }, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data }, { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data }, From 6b7cfdb1d1fc0bd8f252c1f0280cd899e165898c Mon Sep 17 00:00:00 2001 From: bengris32 Date: Mon, 1 Sep 2025 14:30:44 +0100 Subject: [PATCH 069/126] arm64: dts: mediatek: mt8163: Add MMSYS device node Add device node for the Multi Media System (mmsys) on MT8163 SoC. Signed-off-by: bengris32 --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index c6fde272d1d0db..811076be1a1cef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include / { @@ -796,6 +798,17 @@ status = "disabled"; }; + mmsys: syscon@14000000 { + compatible = "mediatek,mt8163-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + #clock-cells = <1>; + #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8163-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; From ac69db758ef515114461b9c73ab7ba1788af0cd7 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Mon, 1 Sep 2025 16:14:45 +0100 Subject: [PATCH 070/126] arm64: dts: mediatek: mt8163: Add M4U, SMI common and LARBs Add device tree nodes for the M4U, SMI common and SMI LARBs on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 67 ++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 811076be1a1cef..bec0238246fec6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -417,6 +418,15 @@ interrupt-controller; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt8163-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + #iommu-cells = <1>; + }; + efuse: efuse@10206000 { compatible = "mediatek,mt8163-efuse", "mediatek,efuse"; reg = <0 0x10206000 0 0x1000>; @@ -809,23 +819,80 @@ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; + larb0: larb@14016000 { + compatible = "mediatek,mt8163-smi-larb"; + reg = <0 0x14016000 0 0x1000>; + interrupts = ; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <0>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + }; + + smi_common: smi@14017000 { + compatible = "mediatek,mt8163-smi-common"; + reg = <0 0x14017000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8163-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; + larb2: larb@15001000 { + compatible = "mediatek,mt8163-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + interrupts = ; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <2>; + clocks = <&imgsys CLK_IMG_LARB2_SMI>, + <&imgsys CLK_IMG_LARB2_SMI>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8163_POWER_DOMAIN_ISP>; + }; + vdecsys: clock-controller@16000000 { compatible = "mediatek,mt8163-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + larb1: larb@16010000 { + compatible = "mediatek,mt8163-smi-larb"; + reg = <0 0x16010000 0 0x10000>; + interrupts = ; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <1>; + clocks = <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB_CKEN>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8163_POWER_DOMAIN_VDEC>; + }; + vencsys: clock-controller@17000000 { compatible = "mediatek,mt8163-vencsys", "syscon"; reg = <0 0x17000000 0 0x1000>; #clock-cells = <1>; }; + + larb3: larb@17001000 { + compatible = "mediatek,mt8163-smi-larb"; + reg = <0 0x17001000 0 0x1000>; + interrupts = ; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <3>; + clocks = <&vencsys CLK_VENC_CKE1>, + <&vencsys CLK_VENC_CKE0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8163_POWER_DOMAIN_VENC>; + }; }; thermal-zones { From 5638291d64eddd7bdba8724c7625b554050435a0 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Thu, 19 Feb 2026 22:37:50 +0000 Subject: [PATCH 071/126] phy: mediatek: mipi: Add optional reset support Add optional reset support to the MediaTek MIPI TX PHY driver. Signed-off-by: Ben Grisdale --- drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c index 065ea626093aaa..1166ac493b0198 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c @@ -3,6 +3,8 @@ * Copyright (c) 2015 MediaTek Inc. */ +#include + #include "phy-mtk-mipi-dsi.h" inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw) @@ -155,6 +157,10 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev) if (ret < 0) return dev_err_probe(dev, ret, "Failed to read clock-output-names\n"); + ret = device_reset_optional(dev); + if (ret < 0) + return ret; + clk_init.ops = mipi_tx->driver_data->mipi_tx_clk_ops; mipi_tx->pll_hw.init = &clk_init; From ce2b169f72e831e86a03d52113f1cbb2ea717347 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Mon, 2 Feb 2026 00:41:57 +0000 Subject: [PATCH 072/126] dt-bindings: phy: mediatek,dsi-phy: Add compatible for MT8163 Add a compatible string for the DSI PHY on the MT8163 SoC. Signed-off-by: bengris32 --- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index c6d0bbdbe0e227..32524e29681b79 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -37,6 +37,7 @@ properties: - mediatek,mt8365-mipi-tx - const: mediatek,mt8183-mipi-tx - const: mediatek,mt2701-mipi-tx + - const: mediatek,mt8163-mipi-tx - const: mediatek,mt8173-mipi-tx - const: mediatek,mt8183-mipi-tx From 6f91ba136229bcd08c633987eb225ab5de222727 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Thu, 19 Feb 2026 22:44:18 +0000 Subject: [PATCH 073/126] phy: mediatek: mipi: mt8163: Add support for MT8163 MIPI TX Add support for the DSI PHY (MIPI TX) on the MT8163 SoC. This SoC's MIPI TX requires it's own unique initialization sequence which is not seen in other SoCs. Signed-off-by: Ben Grisdale --- .../phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 114 ++++++++++++++++++ drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 1 + drivers/phy/mediatek/phy-mtk-mipi-dsi.h | 1 + 3 files changed, 116 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c index 438ff3605d9012..807cab2f9e99da 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c @@ -80,8 +80,12 @@ #define MIPITX_DSI_PLL_CON2 0x58 +#define MIPITX_DSI_PLL_CHG 0x60 +#define RG_DSI_MPPLL_SDM_PCW_CHG BIT(0) + #define MIPITX_DSI_PLL_TOP 0x64 #define RG_DSI_MPPLL_PRESERVE GENMASK(15, 8) +#define RG_DSI_MPPLL_PRESERVE_MT8163 GENMASK(11, 7) #define MIPITX_DSI_PLL_PWR 0x68 #define RG_DSI_MPPLL_SDM_PWR_ON BIT(0) @@ -211,6 +215,101 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw) return 0; } +static int mtk_mipi_tx_pll_prepare_mt8163(struct clk_hw *hw) +{ + struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); + void __iomem *base = mipi_tx->regs; + u8 txdiv, txdiv0, txdiv1; + u32 reg; + u64 pcw; + + dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate); + + if (mipi_tx->data_rate >= 500000000) { + txdiv = 1; + txdiv0 = 0; + txdiv1 = 0; + } else if (mipi_tx->data_rate >= 250000000) { + txdiv = 2; + txdiv0 = 1; + txdiv1 = 0; + } else if (mipi_tx->data_rate >= 125000000) { + txdiv = 4; + txdiv0 = 2; + txdiv1 = 0; + } else if (mipi_tx->data_rate > 62000000) { + txdiv = 8; + txdiv0 = 2; + txdiv1 = 1; + } else if (mipi_tx->data_rate >= 50000000) { + txdiv = 16; + txdiv0 = 2; + txdiv1 = 2; + } else { + return -EINVAL; + } + + for (reg = MIPITX_DSI_CLOCK_LANE; + reg <= MIPITX_DSI_DATA_LANE3; reg += 4) + mtk_phy_update_bits(base + reg, + RG_DSI_LNTx_RT_CODE, + FIELD_PREP(RG_DSI_LNTx_RT_CODE, 0x8)); + + mtk_phy_set_bits(base + MIPITX_DSI_BG_CON, + RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN | + RG_DSI_BG_FAST_CHARGE); + + usleep_range(30, 100); + + mtk_phy_set_bits(base + MIPITX_DSI_TOP_CON, RG_DSI_LNT_HS_BIAS_EN); + + mtk_phy_set_bits(base + MIPITX_DSI_CON, + RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN); + + mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, + RG_DSI_MPPLL_SDM_PWR_ON | RG_DSI_MPPLL_SDM_ISO_EN, + RG_DSI_MPPLL_SDM_PWR_ON); + + mtk_phy_clear_bits(base + MIPITX_DSI_BG_CON, RG_DSI_BG_FAST_CHARGE); + + usleep_range(30, 100); + + mtk_phy_update_bits(base + MIPITX_DSI_PLL_CON0, + RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 | + RG_DSI_MPPLL_PREDIV, + FIELD_PREP(RG_DSI_MPPLL_TXDIV0, txdiv0) | + FIELD_PREP(RG_DSI_MPPLL_TXDIV1, txdiv1)); + + /* + * PLL PCW config + * PCW bit 24~30 = integer part of pcw + * PCW bit 0~23 = fractional part of pcw + * pcw = data_Rate*4*txdiv/(Ref_clk*2); + * Post DIV =4, so need data_Rate*4 + * Ref_clk is 26MHz + */ + pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 26000000); + writel(pcw, base + MIPITX_DSI_PLL_CON2); + + mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_FRA_EN); + + mtk_phy_update_field(base + MIPITX_DSI_PLL_TOP, + RG_DSI_MPPLL_PRESERVE_MT8163, + mipi_tx->driver_data->mppll_preserve); + + mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); + + usleep_range(20, 100); + + mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CHG, RG_DSI_MPPLL_SDM_PCW_CHG); + + mtk_phy_set_bits(base + MIPITX_DSI_PLL_CHG, RG_DSI_MPPLL_SDM_PCW_CHG); + + mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_SSC_EN); + + return 0; +} + static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw) { struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); @@ -253,6 +352,14 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = { .recalc_rate = mtk_mipi_tx_pll_recalc_rate, }; +static const struct clk_ops mtk_mipi_tx_pll_ops_mt8163 = { + .prepare = mtk_mipi_tx_pll_prepare_mt8163, + .unprepare = mtk_mipi_tx_pll_unprepare, + .round_rate = mtk_mipi_tx_pll_round_rate, + .set_rate = mtk_mipi_tx_pll_set_rate, + .recalc_rate = mtk_mipi_tx_pll_recalc_rate, +}; + static void mtk_mipi_tx_power_on_signal(struct phy *phy) { struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); @@ -286,6 +393,13 @@ const struct mtk_mipitx_data mt2701_mipitx_data = { .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, }; +const struct mtk_mipitx_data mt8163_mipitx_data = { + .mppll_preserve = 2, + .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops_mt8163, + .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal, + .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, +}; + const struct mtk_mipitx_data mt8173_mipitx_data = { .mppll_preserve = 0, .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops, diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c index 1166ac493b0198..6e7a4e4686b733 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c @@ -187,6 +187,7 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev) static const struct of_device_id mtk_mipi_tx_match[] = { { .compatible = "mediatek,mt2701-mipi-tx", .data = &mt2701_mipitx_data }, + { .compatible = "mediatek,mt8163-mipi-tx", .data = &mt8163_mipitx_data }, { .compatible = "mediatek,mt8173-mipi-tx", .data = &mt8173_mipitx_data }, { .compatible = "mediatek,mt8183-mipi-tx", .data = &mt8183_mipitx_data }, { /* sentinel */ } diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h index 5d4876f1dc9509..7d570313f10ebe 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h @@ -40,6 +40,7 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate); extern const struct mtk_mipitx_data mt2701_mipitx_data; +extern const struct mtk_mipitx_data mt8163_mipitx_data; extern const struct mtk_mipitx_data mt8173_mipitx_data; extern const struct mtk_mipitx_data mt8183_mipitx_data; From 5a8ce6254453d749d971d8bf39bda5f4d2afd6f3 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 16:56:38 +0000 Subject: [PATCH 074/126] dt-bindings: display: mediatek: ovl: Add compatible for MT8163 Add a compatible string for the OVL block on the MT8163 SoC, this is the same as MT8173. Signed-off-by: bengris32 --- .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 679f731f0f15f7..d4824417c80907 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -37,6 +37,7 @@ properties: - items: - enum: - mediatek,mt6795-disp-ovl + - mediatek,mt8163-disp-ovl - const: mediatek,mt8173-disp-ovl - items: - enum: From e0ed38e70997a51bb46a127a0e850063b83fd66a Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 16:59:27 +0000 Subject: [PATCH 075/126] dt-bindings: display: mediatek: color: Add compatible for MT8163 Add a compatible string for the COLOR block on the MT8163 SoC, this is the same as MT8173. Signed-off-by: bengris32 --- .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index 5564f4063317b2..68d3b068c5d826 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -39,6 +39,7 @@ properties: - items: - enum: - mediatek,mt6795-disp-color + - mediatek,mt8163-disp-color - mediatek,mt8183-disp-color - mediatek,mt8186-disp-color - mediatek,mt8188-disp-color From b400ed450603f2448bdd4ce3ca54ac87618c88cd Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 17:07:07 +0000 Subject: [PATCH 076/126] dt-bindings: display: mediatek: ccorr: Add compatible for MT8163 Add a compatible string for the CCORR block on the MT8163 SoC, which for the sake of this driver, is the same as MT8192. Signed-off-by: bengris32 --- .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 5c5068128d0c7e..c58305a57dc69e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -31,6 +31,7 @@ properties: - const: mediatek,mt8183-disp-ccorr - items: - enum: + - mediatek,mt8163-disp-ccorr - mediatek,mt8186-disp-ccorr - mediatek,mt8188-disp-ccorr - mediatek,mt8195-disp-ccorr From 90d50e2eeaf654fac9c2aa6d3c2ac36071b8f412 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 17:11:17 +0000 Subject: [PATCH 077/126] dt-bindings: display: mediatek: aal: Add compatible for MT8163 Add a compatible string for the AAL block on the MT8163 SoC, which for the sake of this driver, is the same as MT8183 as it does not have the DISP_AAL_GAMMA_LUT register. Signed-off-by: bengris32 --- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 4bbea72b292add..b3f87b67596162 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -37,6 +37,7 @@ properties: - const: mediatek,mt8173-disp-aal - items: - enum: + - mediatek,mt8163-disp-aal - mediatek,mt8186-disp-aal - mediatek,mt8188-disp-aal - mediatek,mt8192-disp-aal From ec3de12dcb9555a4f2624d7047e0c486c07760de Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 17:20:15 +0000 Subject: [PATCH 078/126] dt-bindings: display: mediatek: gamma: Add compatible for MT8163 Add a compatible string for the GAMMA block on the MT8163 SoC. Signed-off-by: bengris32 --- .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index ec1054bb06d461..67c975387de5e9 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -22,6 +22,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt8163-disp-gamma - mediatek,mt8173-disp-gamma - mediatek,mt8183-disp-gamma - mediatek,mt8195-disp-gamma From de0f2c32fddaf36e0c4cbdd4a7e9ad257a9fd4d7 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 17:21:03 +0000 Subject: [PATCH 079/126] drm/mediatek: gamma: Add support for MT8163 gamma The display GAMMA block on the MT8163 SoC is an outlier here: It does not have dither control, nor does it have a GAMMA_LUT_TYPE bit. Add a new has_type field to platform data to account for this. Signed-off-by: bengris32 --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 16 +++++++++++++++- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 8afd15006df2a2..ba34519f02edc0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -44,6 +44,7 @@ struct mtk_disp_gamma_data { bool has_dither; + bool has_type; bool lut_diff; u16 lut_bank_size; u16 lut_size; @@ -189,7 +190,7 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) cfg_val = readl(gamma->regs + DISP_GAMMA_CFG); - if (!gamma->data->has_dither) { + if (gamma->data->has_type) { /* Descending or Rising LUT */ if (mtk_gamma_lut_is_descending(lut, gamma->data->lut_size - 1)) cfg_val |= FIELD_PREP(GAMMA_LUT_TYPE, 1); @@ -293,14 +294,24 @@ static void mtk_disp_gamma_remove(struct platform_device *pdev) component_del(&pdev->dev, &mtk_disp_gamma_component_ops); } +static const struct mtk_disp_gamma_data mt8163_gamma_driver_data = { + .has_dither = false, + .has_type = false, + .lut_bank_size = 512, + .lut_bits = 10, + .lut_size = 512, +}; + static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .has_type = false, .lut_bank_size = 512, .lut_bits = 10, .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { + .has_type = true, .lut_bank_size = 512, .lut_bits = 10, .lut_diff = true, @@ -308,6 +319,7 @@ static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { }; static const struct mtk_disp_gamma_data mt8195_gamma_driver_data = { + .has_type = true, .lut_bank_size = 256, .lut_bits = 12, .lut_diff = true, @@ -315,6 +327,8 @@ static const struct mtk_disp_gamma_data mt8195_gamma_driver_data = { }; static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { + { .compatible = "mediatek,mt8163-disp-gamma", + .data = &mt8163_gamma_driver_data}, { .compatible = "mediatek,mt8173-disp-gamma", .data = &mt8173_gamma_driver_data}, { .compatible = "mediatek,mt8183-disp-gamma", diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 5060edd7f32d54..5d1c689309283a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -749,6 +749,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_DITHER }, { .compatible = "mediatek,mt8195-disp-dsc", .data = (void *)MTK_DISP_DSC }, + { .compatible = "mediatek,mt8163-disp-gamma", + .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8167-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8173-disp-gamma", From 8e98f3da03df6c48d49add51740e2c1de8781717 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 17:24:08 +0000 Subject: [PATCH 080/126] dt-bindings: display: mediatek: dither: Add compatible for MT8163 Add a compatible string for the DITHER block on the MT8163 SoC, which for the sake of this driver, is the same as MT8183. Signed-off-by: bengris32 --- .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 891c95be15b974..b2d6fcf120b05a 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8183-disp-dither - items: - enum: + - mediatek,mt8163-disp-dither - mediatek,mt8167-disp-dither - mediatek,mt8186-disp-dither - mediatek,mt8188-disp-dither From 4e2b71e080f0b6a9d3b29e745c7d5c6e949f5790 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 17:27:57 +0000 Subject: [PATCH 081/126] dt-bindings: display: mediatek: rdma: Add compatible for MT8163 Add a compatible string for the RDMA block on the MT8163 SoC, which for the sake of this driver, is the same as MT8173. Signed-off-by: bengris32 --- .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index cb187a95c11ea4..64c2f27182bf4c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -40,6 +40,7 @@ properties: - const: mediatek,mt2701-disp-rdma - items: - enum: + - mediatek,mt8163-disp-rdma - mediatek,mt6795-disp-rdma - const: mediatek,mt8173-disp-rdma - items: From 86aa5e50190ec988dcafa7b611d2ac4a7dfc1b21 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Thu, 19 Feb 2026 01:43:37 +0000 Subject: [PATCH 082/126] dt-bindings: display: mediatek: ufoe: Add compatible for MT8163 Add a compatible string for the UFOE block on the MT8163 SoC, which for the sake of this driver, is the same as MT8173. Signed-off-by: Ben Grisdale --- .../devicetree/bindings/display/mediatek/mediatek,ufoe.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml index 036a66ed42e739..5842c5873db9ec 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml @@ -25,7 +25,9 @@ properties: - enum: - mediatek,mt8173-disp-ufoe - items: - - const: mediatek,mt6795-disp-ufoe + - enum: + - mediatek,mt8163-disp-ufoe + - mediatek,mt6795-disp-ufoe - const: mediatek,mt8173-disp-ufoe reg: From 2e4c05be709c32c83d21d58d5a81a07d81dd8038 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 20 Feb 2026 16:57:33 +0000 Subject: [PATCH 083/126] dt-bindings: display: mediatek: dsi: Add compatible for MT8163 Add a compatible string for the DSI controller on the MT8163 SoC. Signed-off-by: Ben Grisdale --- .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml index 27ffbccc2a082e..0ac2d51c9a0d19 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -25,6 +25,7 @@ properties: - enum: - mediatek,mt2701-dsi - mediatek,mt7623-dsi + - mediatek,mt8163-dsi - mediatek,mt8167-dsi - mediatek,mt8173-dsi - mediatek,mt8183-dsi From 76c60255103d148b18b4713b5d734d479c1a495a Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 20 Feb 2026 16:50:14 +0000 Subject: [PATCH 084/126] drm/mediatek: dsi: Add support for MT8163 DSI controller Add initial support for the DSI host controller on the MT8163 SoC. This SoC has a unique quirk where DSI_BUSY bit cannot be cleared by writing RACK to DSI_RACK register, which causes the interrupt handler to spin forever. Instead, set the RACK_BYPASS bit for this SoC and add a new flag in the platform data for it. This SoC's DSI host controller also does not signal VM_DONE so add another flag to bypass it. Signed-off-by: Ben Grisdale --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ drivers/gpu/drm/mediatek/mtk_dsi.c | 43 +++++++++++++++++++++----- 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 5d1c689309283a..ec04337e9e04e7 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -841,6 +841,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt8163-dsi", + .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8183-dsi", diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 5aa71fcdcfab78..da6a15619f602b 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -105,6 +105,7 @@ #define DSI_RACK 0x84 #define RACK BIT(0) +#define RACK_BYPASS BIT(1) #define DSI_PHY_LCCON 0x104 #define LC_HS_TX_EN BIT(0) @@ -194,6 +195,8 @@ struct mtk_dsi_driver_data { bool has_size_ctl; bool cmdq_long_packet_ctl; bool support_per_frame_lp; + bool bypass_rack; + bool no_vm_done_irq; }; struct mtk_dsi { @@ -604,9 +607,14 @@ static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi) static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi) { - u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG; + u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG; + + if (!dsi->driver_data->no_vm_done_irq) + inten |= VM_DONE_INT_FLAG; writel(inten, dsi->regs + DSI_INTEN); + if (dsi->driver_data->bypass_rack) + writel(RACK_BYPASS, dsi->regs + DSI_RACK); } static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit) @@ -647,10 +655,12 @@ static irqreturn_t mtk_dsi_irq(int irq, void *dev_id) status = readl(dsi->regs + DSI_INTSTA) & flag; if (status) { - do { - mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK); - tmp = readl(dsi->regs + DSI_INTSTA); - } while (tmp & DSI_BUSY); + if (!dsi->driver_data->bypass_rack) { + do { + mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK); + tmp = readl(dsi->regs + DSI_INTSTA); + } while (tmp & DSI_BUSY); + } mtk_dsi_mask(dsi, DSI_INTSTA, status, 0); mtk_dsi_irq_data_set(dsi, status); @@ -665,12 +675,21 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t) mtk_dsi_irq_data_clear(dsi, irq_flag); mtk_dsi_set_cmd_mode(dsi); - if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) { + /* + * If the DSI engine does not signal a VM done interrupt + * after completing the mode switch then don't wait for it. + * + * Nothing else needs to be done here since mtk_dsi_host_send_cmd() + * would wait for the engine to go idle; this works out because + * DSI_BUSY is always set when running in video mode anyway. + */ + if (!dsi->driver_data->no_vm_done_irq && + !mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) { DRM_ERROR("failed to switch cmd mode\n"); return -ETIME; - } else { - return 0; } + + return 0; } static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) @@ -1265,6 +1284,13 @@ static void mtk_dsi_remove(struct platform_device *pdev) mipi_dsi_host_unregister(&dsi->host); } +static const struct mtk_dsi_driver_data mt8163_dsi_driver_data = { + .reg_cmdq_off = 0x200, + .reg_vm_cmd_off = 0x130, + .bypass_rack = true, + .no_vm_done_irq = true, +}; + static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = { .reg_cmdq_off = 0x200, .reg_vm_cmd_off = 0x130, @@ -1305,6 +1331,7 @@ static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = { static const struct of_device_id mtk_dsi_of_match[] = { { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data }, + { .compatible = "mediatek,mt8163-dsi", .data = &mt8163_dsi_driver_data }, { .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data }, { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data }, { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data }, From 933513f0a4764c41e570969b429a1eae1a931cf4 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 22 Feb 2026 02:09:06 +0000 Subject: [PATCH 085/126] drm/mediatek: dsi: Set DSI_MODE to command mode in mtk_dsi_poweron mtk_dsi_poweron() is called as part of mtk_dsi_bridge_atomic_pre_enable(), which occurs before the HS clock is enabled and before the DSI mode is formally set in mtk_dsi_set_mode(). At this point, it is inappropriate to start the DSI controller in video mode because the panel is likely not yet prepared for a video stream. During this phase, the panel driver typically sends initialization commands, requiring the controller to be in command mode. Since some DSI controllers default to video mode after a hardware reset, they may inadvertently start in the wrong mode. Explicitly call mtk_dsi_set_cmd_mode() during power-on to ensure the controller starts in command mode during the pre-enable phase. Signed-off-by: Ben Grisdale --- drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index da6a15619f602b..d547199d63dad6 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -746,6 +746,12 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) goto err_disable_engine_clk; } + /* + * Some SoC's DSI controllers may default to video mode after + * asserting reset. We need to start in command mode initially + * to be ready for sending initialization commands. + */ + mtk_dsi_set_cmd_mode(dsi); mtk_dsi_enable(dsi); if (dsi->driver_data->has_shadow_ctl) From e9a13795639cf58bccf6cdc82ed370f2eaf53aa1 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 17:40:40 +0000 Subject: [PATCH 086/126] dt-bindings: pwm: Add compatible for MT8163 Display PWM Add a compatible string for the PWM block on the MT8163 SoC, this is the same as MT8173. Signed-off-by: bengris32 --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 68ef30414325a5..c88663f3d6fca9 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -23,6 +23,7 @@ properties: - items: - enum: - mediatek,mt6795-disp-pwm + - mediatek,mt8163-disp-pwm - mediatek,mt8167-disp-pwm - const: mediatek,mt8173-disp-pwm - items: From 9ba27ed0575a1ce03dbd62b134e5dab8f8e8ee77 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 17:45:13 +0000 Subject: [PATCH 087/126] dt-bindings: soc: mediatek: Add compatible for MT8163 display mutex Add a compatible string for the display mutex on the MT8163 SoC. Signed-off-by: bengris32 --- .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 5267cfe92572dd..5d5c900b2756e5 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt2701-disp-mutex - mediatek,mt2712-disp-mutex - mediatek,mt6795-disp-mutex + - mediatek,mt8163-disp-mutex - mediatek,mt8167-disp-mutex - mediatek,mt8173-disp-mutex - mediatek,mt8183-disp-mutex From c1349c692156307f0e93aa5f6041653f82f92b6a Mon Sep 17 00:00:00 2001 From: bengris32 Date: Wed, 3 Sep 2025 21:37:47 +0100 Subject: [PATCH 088/126] soc: mtk-mutex: Add support for MT8163 display mutex Signed-off-by: bengris32 --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ drivers/soc/mediatek/mtk-mutex.c | 40 ++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index ec04337e9e04e7..b3d5dbe7d729d6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -765,6 +765,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8163-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8167-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 38179e8cd98f84..9e047df8b92ed4 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -66,6 +66,20 @@ #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6) #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6) +#define MT8163_MUTEX_MOD_DISP_OVL0 6 +#define MT8163_MUTEX_MOD_DISP_OVL1 7 +#define MT8163_MUTEX_MOD_DISP_RDMA0 8 +#define MT8163_MUTEX_MOD_DISP_RDMA1 9 +#define MT8163_MUTEX_MOD_DISP_WDMA0 10 +#define MT8163_MUTEX_MOD_DISP_COLOR0 11 +#define MT8163_MUTEX_MOD_DISP_CCORR 12 +#define MT8163_MUTEX_MOD_DISP_AAL 13 +#define MT8163_MUTEX_MOD_DISP_GAMMA 14 +#define MT8163_MUTEX_MOD_DISP_DITHER 15 +#define MT8163_MUTEX_MOD_DISP_UFOE 16 +#define MT8163_MUTEX_MOD_DISP_PWM0 17 +#define MT8163_MUTEX_MOD_DISP_WDMA1 18 + #define MT8167_MUTEX_MOD_DISP_PWM 1 #define MT8167_MUTEX_MOD_DISP_OVL0 6 #define MT8167_MUTEX_MOD_DISP_OVL1 7 @@ -397,6 +411,22 @@ static const u8 mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, }; +static const u8 mt8163_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8163_MUTEX_MOD_DISP_AAL, + [DDP_COMPONENT_COLOR0] = MT8163_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER0] = MT8163_MUTEX_MOD_DISP_DITHER, + [DDP_COMPONENT_CCORR] = MT8163_MUTEX_MOD_DISP_CCORR, + [DDP_COMPONENT_GAMMA] = MT8163_MUTEX_MOD_DISP_GAMMA, + [DDP_COMPONENT_OVL0] = MT8163_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT8163_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT8163_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_RDMA0] = MT8163_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8163_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_UFOE] = MT8163_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT8163_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_WDMA1] = MT8163_MUTEX_MOD_DISP_WDMA1, +}; + static const u8 mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, @@ -754,6 +784,15 @@ static const struct mtk_mutex_data mt6795_mutex_driver_data = { .mutex_sof_reg = MT2701_MUTEX0_SOF0, }; +static const struct mtk_mutex_data mt8163_mutex_driver_data = { + .mutex_mod = mt8163_mutex_mod, + .mutex_sof = mt8167_mutex_sof, + .mutex_mod_reg = MT2701_MUTEX0_MOD0, + .mutex_mod1_reg = MT2701_MUTEX0_MOD1, + .mutex_sof_reg = MT2701_MUTEX0_SOF0, + .no_clk = true, +}; + static const struct mtk_mutex_data mt8167_mutex_driver_data = { .mutex_mod = mt8167_mutex_mod, .mutex_sof = mt8167_mutex_sof, @@ -1133,6 +1172,7 @@ static const struct of_device_id mutex_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_mutex_driver_data }, { .compatible = "mediatek,mt2712-disp-mutex", .data = &mt2712_mutex_driver_data }, { .compatible = "mediatek,mt6795-disp-mutex", .data = &mt6795_mutex_driver_data }, + { .compatible = "mediatek,mt8163-disp-mutex", .data = &mt8163_mutex_driver_data }, { .compatible = "mediatek,mt8167-disp-mutex", .data = &mt8167_mutex_driver_data }, { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data }, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data }, From f261e6b03d23df739242bc5c34c0cc9bf33017c0 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 17:49:19 +0000 Subject: [PATCH 089/126] arm64: dts: mediatek: mt8163: Add display blocks and DSI Add all device tree nodes for the display components defined in the primary display path on the MT8163 SoC. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 132 +++++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index bec0238246fec6..83676d180f88e1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -29,6 +29,17 @@ interrupt-parent = <&sysirq>; compatible = "mediatek,mt8163"; + aliases { + aal0 = &aal; + ccorr0 = &ccorr; + color0 = &color; + dither0 = &dither; + dsi0 = &dsi; + ovl0 = &ovl0; + pwm0 = &pwm0; + rdma0 = &rdma0; + }; + cluster0_opp: opp-table-cluster0 { compatible = "operating-points-v2"; opp-shared; @@ -454,6 +465,17 @@ #mbox-cells = <2>; }; + mipi_tx0: dsi-phy@10215000 { + compatible = "mediatek,mt8163-mipi-tx"; + reg = <0 0x10215000 0 0x1000>; + clocks = <&apmixedsys CLK_APMIXED_MIPI_26M>; + clock-output-names = "mipi_tx0_pll"; + resets = <&infracfg MT8163_INFRA_RST0_MIPI_D>; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@10221000 { compatible = "arm,gic-400"; reg = <0 0x10221000 0 0x1000>, @@ -819,6 +841,116 @@ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; + ovl0: ovl@14007000 { + compatible = "mediatek,mt8163-disp-ovl", "mediatek,mt8173-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + }; + + rdma0: dma-controller@14009000 { + compatible = "mediatek,mt8163-disp-rdma", "mediatek,mt8173-disp-rdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; + + color: color@1400c000 { + compatible = "mediatek,mt8163-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + ccorr: ccorr@1400d000 { + compatible = "mediatek,mt8163-disp-ccorr", "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_CCORR>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + }; + + aal: aal@1400e000 { + compatible = "mediatek,mt8163-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_AAL>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + gamma: gamma@1400f000 { + compatible = "mediatek,mt8163-disp-gamma"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + }; + + dither: dither@14010000 { + compatible = "mediatek,mt8163-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x14010000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_DITHER>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x0000 0x1000>; + }; + + ufoe: ufoe@14011000 { + compatible = "mediatek,mt8163-disp-ufoe", "mediatek,mt8173-disp-ufoe"; + reg = <0 0x14011000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_UFOE>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + }; + + dsi: dsi@14012000 { + compatible = "mediatek,mt8163-dsi"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, + <&mmsys CLK_MM_DSI_DIGITAL>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8163_MMSYS_RST_DSI>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + pwm0: pwm@14014000 { + compatible = "mediatek,mt8163-disp-pwm", "mediatek,mt8173-disp-pwm"; + reg = <0 0x14014000 0 0x1000>; + #pwm-cells = <2>; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_PWM_26M>, + <&mmsys CLK_MM_DISP_PWM_MM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + mutex: mutex@14015000 { + compatible = "mediatek,mt8163-disp-mutex"; + reg = <0 0x14015000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8163_POWER_DOMAIN_MM>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; + mediatek,gce-events = , + ; + }; + larb0: larb@14016000 { compatible = "mediatek,mt8163-smi-larb"; reg = <0 0x14016000 0 0x1000>; From 6661948117bd26849a423cfa2b06f1eda1b7fe50 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 29 Aug 2025 12:30:04 +0100 Subject: [PATCH 090/126] dt-bindings: arm: Add compatibles for MT8163 SoC and Amazon MT8163 family Document compatibles for the MT8163 SoC and the Amazon devices which are known to use it. Co-authored-by: Jack Matthews Signed-off-by: Ben Grisdale Signed-off-by: Jack Matthews --- .../devicetree/bindings/arm/mediatek.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 382d0eb4d0af6d..cc4c65fed32c14 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -128,6 +128,21 @@ properties: - enum: - mediatek,mt8135-evbp1 - const: mediatek,mt8135 + - items: + - enum: + - amazon,biscuit + - amazon,checkers + - amazon,cronos-v4.1 + - amazon,cronos-v4.2 + - amazon,cronos-v4.3 + - amazon,cronos + - amazon,crown + - amazon,douglas + - amazon,giza + - amazon,karnak + - amazon,mustang + - amazon,rook + - const: mediatek,mt8163 - items: - enum: - mediatek,mt8167-pumpkin From df1776fae83e330651e63eed31ba08d31801e19a Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Thu, 11 Dec 2025 19:21:26 +0000 Subject: [PATCH 091/126] arm64: dts: mediatek: Add basic support for Amazon MT8163 devices Add basic support for the Amazon MT8163 family of devices. Currently, the devices are able to boot to a working serial console over UART0. Co-authored-by: Jack Matthews Signed-off-by: Ben Grisdale Signed-off-by: Jack Matthews --- arch/arm64/boot/dts/mediatek/Makefile | 12 +++++ .../dts/mediatek/mt8163-amazon-biscuit.dts | 13 +++++ .../dts/mediatek/mt8163-amazon-checkers.dts | 14 ++++++ .../dts/mediatek/mt8163-amazon-common.dtsi | 48 +++++++++++++++++++ .../mediatek/mt8163-amazon-cronos-v4.1.dts | 14 ++++++ .../mediatek/mt8163-amazon-cronos-v4.2.dts | 14 ++++++ .../mediatek/mt8163-amazon-cronos-v4.3.dts | 14 ++++++ .../dts/mediatek/mt8163-amazon-cronos.dts | 14 ++++++ .../dts/mediatek/mt8163-amazon-cronos.dtsi | 7 +++ .../boot/dts/mediatek/mt8163-amazon-crown.dts | 14 ++++++ .../dts/mediatek/mt8163-amazon-douglas.dts | 13 +++++ .../boot/dts/mediatek/mt8163-amazon-giza.dts | 13 +++++ .../dts/mediatek/mt8163-amazon-karnak.dts | 13 +++++ .../dts/mediatek/mt8163-amazon-mustang.dts | 13 +++++ .../boot/dts/mediatek/mt8163-amazon-rook.dts | 13 +++++ .../boot/dts/mediatek/mt8163-amazon-show.dtsi | 7 +++ 16 files changed, 236 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.1.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.2.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.3.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-crown.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-douglas.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-giza.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-karnak.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-mustang.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 387faa9c2a09b5..8ed8405accf9b6 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -84,6 +84,18 @@ mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18-dtbs := \ mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \ mt7988a-bananapi-bpi-r4-pro-cn18.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-biscuit.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-checkers.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-cronos-v4.1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-cronos-v4.2.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-cronos-v4.3.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-cronos.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-crown.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-douglas.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-giza.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-karnak.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-mustang.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-rook.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts new file mode 100644 index 00000000000000..2f8d6f77bed187 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +/dts-v1/; +#include "mt8163-amazon-common.dtsi" + +/ { + model = "Amazon Echo Dot (2016)"; + compatible = "amazon,biscuit", "mediatek,mt8163"; + chassis-type = "embedded"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts new file mode 100644 index 00000000000000..786a2827256d01 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + * Copyright (c) 2025-2026 Jack Matthews + */ + +/dts-v1/; +#include "mt8163-amazon-show.dtsi" + +/ { + model = "Amazon Echo Show 5 (2019)"; + compatible = "amazon,checkers", "mediatek,mt8163"; + chassis-type = "embedded"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi new file mode 100644 index 00000000000000..c9cdce2b215dee --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include "mt8163.dtsi" + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000 0 0x20000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_default>; + status = "okay"; +}; + +&pio { + uart0_pins_default: uart0-pins { + pins { + pinmux = , + ; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.1.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.1.dts new file mode 100644 index 00000000000000..cdde96e608818e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.1.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + * Copyright (c) 2025-2026 Jack Matthews + */ + +/dts-v1/; +#include "mt8163-amazon-cronos.dtsi" + +/ { + model = "Amazon Echo Show 5 (2021) (v4.1)"; + compatible = "amazon,cronos-v4.1", "amazon,cronos", "mediatek,mt8163"; + chassis-type = "embedded"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.2.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.2.dts new file mode 100644 index 00000000000000..5882cf6abe9126 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + * Copyright (c) 2025-2026 Jack Matthews + */ + +/dts-v1/; +#include "mt8163-amazon-cronos.dtsi" + +/ { + model = "Amazon Echo Show 5 (2021) (v4.2)"; + compatible = "amazon,cronos-v4.2", "amazon,cronos", "mediatek,mt8163"; + chassis-type = "embedded"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.3.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.3.dts new file mode 100644 index 00000000000000..cb96ffe29b02a9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.3.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + * Copyright (c) 2025-2026 Jack Matthews + */ + +/dts-v1/; +#include "mt8163-amazon-cronos.dtsi" + +/ { + model = "Amazon Echo Show 5 (2021) (v4.3)"; + compatible = "amazon,cronos-v4.3", "amazon,cronos", "mediatek,mt8163"; + chassis-type = "embedded"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dts new file mode 100644 index 00000000000000..1393630b4b1754 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + * Copyright (c) 2025-2026 Jack Matthews + */ + +/dts-v1/; +#include "mt8163-amazon-cronos.dtsi" + +/ { + model = "Amazon Echo Show 5 (2021)"; + compatible = "amazon,cronos", "mediatek,mt8163"; + chassis-type = "embedded"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dtsi new file mode 100644 index 00000000000000..88b2d6793d4955 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + * Copyright (c) 2025-2026 Jack Matthews + */ + +#include "mt8163-amazon-show.dtsi" diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-crown.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-crown.dts new file mode 100644 index 00000000000000..0dd104cd527df7 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-crown.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + * Copyright (c) 2025-2026 Jack Matthews + */ + +/dts-v1/; +#include "mt8163-amazon-show.dtsi" + +/ { + model = "Amazon Echo Show 8 (2019)"; + compatible = "amazon,crown", "mediatek,mt8163"; + chassis-type = "embedded"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-douglas.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-douglas.dts new file mode 100644 index 00000000000000..f3fe13a2e27646 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-douglas.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +/dts-v1/; +#include "mt8163-amazon-common.dtsi" + +/ { + model = "Amazon Fire HD 8 (2017)"; + compatible = "amazon,douglas", "mediatek,mt8163"; + chassis-type = "tablet"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-giza.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-giza.dts new file mode 100644 index 00000000000000..f219beb29183d2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-giza.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +/dts-v1/; +#include "mt8163-amazon-common.dtsi" + +/ { + model = "Amazon Fire HD 8 (2016)"; + compatible = "amazon,giza", "mediatek,mt8163"; + chassis-type = "tablet"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-karnak.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-karnak.dts new file mode 100644 index 00000000000000..eafe05eee56c97 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-karnak.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +/dts-v1/; +#include "mt8163-amazon-common.dtsi" + +/ { + model = "Amazon Fire HD 8 (2018)"; + compatible = "amazon,karnak", "mediatek,mt8163"; + chassis-type = "tablet"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-mustang.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-mustang.dts new file mode 100644 index 00000000000000..4a22bb7eeb42db --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-mustang.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +/dts-v1/; +#include "mt8163-amazon-common.dtsi" + +/ { + model = "Amazon Fire 7 (2019)"; + compatible = "amazon,mustang", "mediatek,mt8163"; + chassis-type = "tablet"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts new file mode 100644 index 00000000000000..2fa4285f74d7f8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +/dts-v1/; +#include "mt8163-amazon-common.dtsi" + +/ { + model = "Amazon Echo Spot (2017)"; + compatible = "amazon,rook", "mediatek,mt8163"; + chassis-type = "embedded"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi new file mode 100644 index 00000000000000..a57980d70375d6 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + * Copyright (c) 2025-2026 Jack Matthews + */ + +#include "mt8163-amazon-common.dtsi" From e55e3c02bf4a5010463f9774287c4cc2b3f76a05 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 12 Dec 2025 15:15:56 +0000 Subject: [PATCH 092/126] arm64: dts: mediatek: mt8163-amazon: Enable PMIC Enable the MT6323 PMIC found on the MT8163 SoC by including the MT6323 device tree and providing the required interrupt. Also set the regulator-always-on and regulator-boot-on properties on regulators providing power to critical components such as the CPU, RTC, system (XO) clock and memory. Signed-off-by: Ben Grisdale --- .../dts/mediatek/mt8163-amazon-common.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi index c9cdce2b215dee..56b2bef587f561 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi @@ -4,6 +4,7 @@ */ #include "mt8163.dtsi" +#include "mt6323.dtsi" / { aliases { @@ -32,6 +33,35 @@ }; }; +&mt6323_vproc_reg { + regulator-always-on; + regulator-boot-on; +}; + +&mt6323_vsys_reg { + regulator-always-on; + regulator-boot-on; +}; + +&mt6323_vm_reg { + regulator-always-on; + regulator-boot-on; +}; + +&mt6323_vrtc_reg { + regulator-always-on; + regulator-boot-on; +}; + +&mt6323_vtcxo_reg { + regulator-always-on; + regulator-boot-on; +}; + +&pmic { + interrupts-extended = <&pio 24 IRQ_TYPE_LEVEL_HIGH>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_default>; From 069ba314a4f19c0975f78d876ff110b87c76bfcd Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 12 Dec 2025 19:16:52 +0000 Subject: [PATCH 093/126] arm64: dts: mediatek: mt8163-amazon: Enable eMMC Add required pin configurations and enable the MMC0 controller on Amazon MT8163 devices, which is connected to the eMMC chip on these devices. Signed-off-by: Ben Grisdale --- .../dts/mediatek/mt8163-amazon-common.dtsi | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi index 56b2bef587f561..73d8126ddfabbb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi @@ -58,6 +58,24 @@ regulator-boot-on; }; +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + status = "okay"; + bus-width = <8>; + mediatek,latch-ck = <1>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + cap-mmc-hw-reset; + vmmc-supply = <&mt6323_vemc3v3_reg>; + vqmmc-supply = <&mt6323_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + non-removable; +}; + &pmic { interrupts-extended = <&pio 24 IRQ_TYPE_LEVEL_HIGH>; }; @@ -69,6 +87,60 @@ }; &pio { + mmc0_pins_default: emmc-sdr-pins { + pins_cmd_dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + pins_clk { + pinmux = ; + bias-pull-down; + }; + + pins_rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: emmc-uhs-pins { + pins_cmd_dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins_rst { + pinmux = ; + bias-pull-up; + }; + }; + uart0_pins_default: uart0-pins { pins { pinmux = , From e019985ec617a392336fa19be3c9ccea91d32f9c Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 12 Dec 2025 19:32:40 +0000 Subject: [PATCH 094/126] arm64: dts: mediatek: mt8163-amazon: Enable CPUFreq Enable CPUFreq on Amazon MT8163 devices by adding the required pin configuration for the I2C1 bus and defining the external SYM827 buck as the proc-supply which provides power to the CPUs. Signed-off-by: Ben Grisdale --- .../dts/mediatek/mt8163-amazon-common.dtsi | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi index 73d8126ddfabbb..0e81fcbe745ca1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi @@ -33,6 +33,41 @@ }; }; +&cpu0 { + proc-supply = <&sym827_vproc>; +}; + +&cpu1 { + proc-supply = <&sym827_vproc>; +}; + +&cpu2 { + proc-supply = <&sym827_vproc>; +}; + +&cpu3 { + proc-supply = <&sym827_vproc>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_default>; + status = "okay"; + + sym827_vproc: regulator@60 { + compatible = "silergy,sym827"; + reg = <0x60>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "sym827-vproc"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-enable-ramp-delay = <400>; + regulator-ramp-delay = <8000>; + regulator-always-on; + }; +}; + &mt6323_vproc_reg { regulator-always-on; regulator-boot-on; @@ -87,6 +122,14 @@ }; &pio { + i2c1_pins_default: i2c1-pins { + pins { + pinmux = , + ; + bias-disable; + }; + }; + mmc0_pins_default: emmc-sdr-pins { pins_cmd_dat { pinmux = , From 92074f81cea7a5c02cf90c5bdd34ee47fa2fe340 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 12 Dec 2025 19:50:40 +0000 Subject: [PATCH 095/126] arm64: dts: mediatek: mt8163-amazon: Enable GPU Enable and define a dummy regulator for the Mali GPU which is fixed at 1.15 volts, according to the downstream GPUFreq driver, which doesn't do any voltage scaling. Signed-off-by: Ben Grisdale --- .../boot/dts/mediatek/mt8163-amazon-common.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi index 0e81fcbe745ca1..1a798e1e9c4a7b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi @@ -31,6 +31,15 @@ no-map; }; }; + + vgpu_1v15: regulator-vgpu { + compatible = "regulator-fixed"; + regulator-name = "vgpu_1v15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; }; &cpu0 { @@ -49,6 +58,11 @@ proc-supply = <&sym827_vproc>; }; +&gpu { + status = "okay"; + mali-supply = <&vgpu_1v15>; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; From 782e312d410d385d6cc62e0b02fe5531c21c9f14 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 27 Dec 2025 19:49:13 +0000 Subject: [PATCH 096/126] arm64: dts: mediatek: mt8163-amazon: Reserve memory for AFE Signed-off-by: Ben Grisdale --- .../arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi index 1a798e1e9c4a7b..d9929dd78b1b71 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi @@ -25,6 +25,13 @@ #size-cells = <2>; ranges; + afe_dma_mem: audio-dma-pool { + compatible = "shared-dma-pool"; + size = <0 0x100000>; + alignment = <0 0x10>; + no-map; + }; + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ bl31_secmon_reserved: secmon@43000000 { reg = <0 0x43000000 0 0x30000>; @@ -42,6 +49,10 @@ }; }; +&afe { + memory-region = <&afe_dma_mem>; +}; + &cpu0 { proc-supply = <&sym827_vproc>; }; From c8264113f84bf26c10cf18fa83d961aaee950b66 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 12 Dec 2025 20:11:33 +0000 Subject: [PATCH 097/126] arm64: dts: mediatek: mt8163-amazon-biscuit: Enable USB Signed-off-by: Ben Grisdale --- .../boot/dts/mediatek/mt8163-amazon-biscuit.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts index 2f8d6f77bed187..35e7aec0858e8a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts @@ -11,3 +11,17 @@ compatible = "amazon,biscuit", "mediatek,mt8163"; chassis-type = "embedded"; }; + +&mt6323_vusb_reg { + regulator-always-on; +}; + +&u2phy0 { + status = "okay"; +}; + +&usb0 { + /* No 5V supply for OTG support. */ + dr_mode = "peripheral"; + status = "okay"; +}; From b8b4dedd93867448f91143a6c9be79e4c8bf7ffb Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 12 Dec 2025 20:10:58 +0000 Subject: [PATCH 098/126] arm64: dts: mediatek: mt8163-amazon-rook: Enable USB Signed-off-by: Ben Grisdale --- .../boot/dts/mediatek/mt8163-amazon-rook.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts index 2fa4285f74d7f8..a2eb30bf59f619 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts @@ -11,3 +11,23 @@ compatible = "amazon,rook", "mediatek,mt8163"; chassis-type = "embedded"; }; + +&mt6323_vusb_reg { + regulator-always-on; +}; + +&u2phy0 { + status = "okay"; +}; + +&usb0 { + /* No 5V supply for OTG support. */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb1 { + /* For internal Wi-Fi adapter */ + dr_mode = "host"; + status = "okay"; +}; From 5dcec181470854ab91f5c4cb0ced6f6779e3d32b Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 12 Dec 2025 20:18:58 +0000 Subject: [PATCH 099/126] arm64: dts: mediatek: mt8163-amazon-rook: Add Wi-Fi rfkill device GPIO 27 is wired to control power of the BCM43566 Wi-Fi chip on rook. Signed-off-by: Ben Grisdale --- .../boot/dts/mediatek/mt8163-amazon-rook.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts index a2eb30bf59f619..0914f7c39bb5d9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts @@ -4,12 +4,23 @@ */ /dts-v1/; +#include + #include "mt8163-amazon-common.dtsi" / { model = "Amazon Echo Spot (2017)"; compatible = "amazon,rook", "mediatek,mt8163"; chassis-type = "embedded"; + + rfkill { + compatible = "rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwr_pins>; + label = "rfkill-usb-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&pio 27 GPIO_ACTIVE_HIGH>; + }; }; &mt6323_vusb_reg { @@ -31,3 +42,11 @@ dr_mode = "host"; status = "okay"; }; + +&pio { + wifi_pwr_pins: wifi-pwr-pins { + pins { + pinmux = ; + }; + }; +}; From 93315868366151ba6e4831fe97a29d2e8eeb6eed Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 12 Dec 2025 20:22:02 +0000 Subject: [PATCH 100/126] arm64: dts: mediatek: mt8163-amazon-rook: Add GPIO keys Add GPIO keys for the volume down and volume up buttons on rook. Signed-off-by: Ben Grisdale --- .../boot/dts/mediatek/mt8163-amazon-rook.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts index 0914f7c39bb5d9..9fd18c97125821 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include "mt8163-amazon-common.dtsi" @@ -13,6 +14,26 @@ compatible = "amazon,rook", "mediatek,mt8163"; chassis-type = "embedded"; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pio 37 GPIO_ACTIVE_LOW>; + debounce-interval = <20>; + }; + + key-volume-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pio 50 GPIO_ACTIVE_LOW>; + debounce-interval = <20>; + }; + }; + rfkill { compatible = "rfkill-gpio"; pinctrl-names = "default"; @@ -44,6 +65,15 @@ }; &pio { + gpio_keys_pins: gpio-keys-pins { + pins { + pinmux = , + ; + bias-pull-up; + input-enable; + }; + }; + wifi_pwr_pins: wifi-pwr-pins { pins { pinmux = ; From 2b6866fa8011372dbe6a500ecff7afe98e3baa5a Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 13 Dec 2025 00:53:28 +0000 Subject: [PATCH 101/126] arm64: dts: mediatek: mt8163-amazon-rook: Set version property Stock bootloader checks for this property. Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts index 9fd18c97125821..dd2c5faa35cb8d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts @@ -14,6 +14,9 @@ compatible = "amazon,rook", "mediatek,mt8163"; chassis-type = "embedded"; + /* Needed by stock bootloader */ + version = "evt"; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; From 569b92b3144571d298ac97fe3612370ecf7aa9cd Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 13 Dec 2025 13:50:43 +0000 Subject: [PATCH 102/126] arm64: dts: mediatek: mt8163-amazon-biscuit: Set version property Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts index 35e7aec0858e8a..ef17af08d498a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts @@ -10,6 +10,9 @@ model = "Amazon Echo Dot (2016)"; compatible = "amazon,biscuit", "mediatek,mt8163"; chassis-type = "embedded"; + + /* Needed by stock bootloader */ + version = "evt"; }; &mt6323_vusb_reg { From 2bdf2fd76fbde65539c69724c71344708737e1d8 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Thu, 18 Dec 2025 20:31:56 +0000 Subject: [PATCH 103/126] arm64: dts: mediatek: mt8163-amazon-biscuit: Disable unused hardware Disable all display related hardware blocks on biscuit as they are unused. Also disable the Mali GPU as it seems to either be fused off or not present on the MT8163 variant used on biscuit. This is done in a new mt8163-headless.dtsi file so other headless MT8163 devices (should they exist) can include it in their device trees. Thermal is also disabled on biscuit specifically as the ADC sensors on aren't present. Signed-off-by: Ben Grisdale --- .../dts/mediatek/mt8163-amazon-biscuit.dts | 5 + .../boot/dts/mediatek/mt8163-headless.dtsi | 92 +++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-headless.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts index ef17af08d498a6..5bef59cb6a00b5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mt8163-amazon-common.dtsi" +#include "mt8163-headless.dtsi" / { model = "Amazon Echo Dot (2016)"; @@ -19,6 +20,10 @@ regulator-always-on; }; +&thermal { + status = "disabled"; +}; + &u2phy0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-headless.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-headless.dtsi new file mode 100644 index 00000000000000..6a067112a40f9c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-headless.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2026 Ben Grisdale + */ + +&gpu { + status = "disabled"; +}; + +&gce { + status = "disabled"; +}; + +&mfgcfg { + status = "disabled"; +}; + +&thermal { + status = "disabled"; +}; + +&vdecsys { + status = "disabled"; +}; + +&vencsys { + status = "disabled"; +}; + +&mmsys { + status = "disabled"; +}; + +&iommu { + status = "disabled"; +}; + +&smi_common { + status = "disabled"; +}; + +&larb0 { + status = "disabled"; +}; + +&larb1 { + status = "disabled"; +}; + +&larb2 { + status = "disabled"; +}; + +&larb3 { + status = "disabled"; +}; + +&ovl0 { + status = "disabled"; +}; + +&rdma0 { + status = "disabled"; +}; + +&color { + status = "disabled"; +}; + +&ccorr { + status = "disabled"; +}; + +&aal { + status = "disabled"; +}; + +&gamma { + status = "disabled"; +}; + +&dither { + status = "disabled"; +}; + +&ufoe { + status = "disabled"; +}; + +&mutex { + status = "disabled"; +}; From 0e80077fce16d74b01c87c50bc353b6d5979c49f Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Thu, 18 Dec 2025 20:49:59 +0000 Subject: [PATCH 104/126] arm64: dts: mediatek: mt8163-amazon-biscuit: Add GPIO keys Add GPIO keys for the volume down and volume up buttons on biscuit. Signed-off-by: Ben Grisdale --- .../dts/mediatek/mt8163-amazon-biscuit.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts index 5bef59cb6a00b5..73a6fa408f9ca3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts @@ -4,6 +4,10 @@ */ /dts-v1/; +#include +#include +#include + #include "mt8163-amazon-common.dtsi" #include "mt8163-headless.dtsi" @@ -14,6 +18,19 @@ /* Needed by stock bootloader */ version = "evt"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins_default>; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pio 50 GPIO_ACTIVE_LOW>; + debounce-interval = <20>; + }; + }; }; &mt6323_vusb_reg { @@ -33,3 +50,13 @@ dr_mode = "peripheral"; status = "okay"; }; + +&pio { + gpio_keys_pins_default: gpio-keys-pins { + pins { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; +}; From 30698613d494a878470ddc15d1b07f00ec88c7c9 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Fri, 19 Dec 2025 16:29:12 +0000 Subject: [PATCH 105/126] arm64: dts: mediatek: mt8163-amazon-biscuit: Add keypad Mux the volume down and action button to the keypad controller and enable it. The action button is mapped to KEY_ASSISTANT to try and retain its original purpose. Signed-off-by: Ben Grisdale --- .../dts/mediatek/mt8163-amazon-biscuit.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts index 73a6fa408f9ca3..1eee8612b2659d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-biscuit.dts @@ -33,6 +33,20 @@ }; }; +&keypad { + linux,keymap = ; + + keypad,num-rows = <1>; + keypad,num-columns = <2>; + debounce-delay-ms = <20>; + + pinctrl-names = "default"; + pinctrl-0 = <&keypad_pins_default>; + + status = "okay"; +}; + &mt6323_vusb_reg { regulator-always-on; }; @@ -59,4 +73,12 @@ input-enable; }; }; + + keypad_pins_default: keypad-pins { + pins { + pinmux = , + ; + input-enable; + }; + }; }; From 2b8f29e34fc5bb9e62403a44b83b74380909b483 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Mon, 9 Feb 2026 18:40:14 +0000 Subject: [PATCH 106/126] Input: goodix: Avoid overriding DT provided touch properties The goodix driver allows the max_x and max_y properties to be overriden from the device tree so long as the read config from the touch controller is valid. If that is not the case however, then the driver will override max_x and max_y to default values regardless of whether they are actually valid or not. Fix this by checking again if max_x and max_y are invalid, and if so then set them to safe defaults, but otherwise, use the values parsed from the device tree. Signed-off-by: Ben Grisdale --- drivers/input/touchscreen/goodix.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/goodix.c b/drivers/input/touchscreen/goodix.c index f8798d11ec030f..985e4d92bd8879 100644 --- a/drivers/input/touchscreen/goodix.c +++ b/drivers/input/touchscreen/goodix.c @@ -1190,8 +1190,14 @@ static int goodix_configure_dev(struct goodix_ts_data *ts) dev_err(&ts->client->dev, "Invalid config (%d, %d, %d), using defaults\n", ts->prop.max_x, ts->prop.max_y, ts->max_touch_num); - ts->prop.max_x = GOODIX_MAX_WIDTH - 1; - ts->prop.max_y = GOODIX_MAX_HEIGHT - 1; + + /* Device tree may provide valid values for max_x and max_y + * so check if they are valid, and if so, do not override them. + */ + if (!ts->prop.max_x || !ts->prop.max_y) { + ts->prop.max_x = GOODIX_MAX_WIDTH - 1; + ts->prop.max_y = GOODIX_MAX_HEIGHT - 1; + } ts->max_touch_num = GOODIX_MAX_CONTACTS; input_abs_set_max(ts->input_dev, ABS_MT_POSITION_X, ts->prop.max_x); From 1e8eeadafde5606a75e2bd775f3773c956a90455 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 13 Dec 2025 19:22:44 +0000 Subject: [PATCH 107/126] arm64: dts: mediatek: mt8163-amazon-rook: Enable GT5688 touch Signed-off-by: Ben Grisdale --- .../boot/dts/mediatek/mt8163-amazon-rook.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts index dd2c5faa35cb8d..5d5798e7e0e3ee 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts @@ -47,6 +47,32 @@ }; }; +&i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_default>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt5688"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + interrupt-parent = <&pio>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&pio 89 GPIO_ACTIVE_HIGH>; + irq-gpios = <&pio 49 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <480>; + touchscreen-size-y = <480>; + AVDD28-supply = <&mt6323_vibr_reg>; + }; +}; + +&mt6323_vibr_reg { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + &mt6323_vusb_reg { regulator-always-on; }; @@ -77,6 +103,27 @@ }; }; + i2c0_pins_default: i2c0-pins { + pins { + pinmux = , + ; + bias-disable; + }; + }; + + touch_pins: touch-pins { + pins-irq { + pinmux = ; + bias-pull-up; + input-enable; + }; + + pins-rst { + pinmux = ; + output-high; + }; + }; + wifi_pwr_pins: wifi-pwr-pins { pins { pinmux = ; From ba2a568df05d0724d2779e15ccb5e528fc5ba4b3 Mon Sep 17 00:00:00 2001 From: bengris32 Date: Wed, 3 Sep 2025 21:53:55 +0100 Subject: [PATCH 108/126] drm: panel: Add driver for Amazon Rook HX8379C panels TODO: Currently these panels misbehave when resetting DSI blocks, for now we avoid resetting them and try to retain LK's initialization as done in the downstream driver. Signed-off-by: Ben Grisdale --- drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile | 1 + .../panel/panel-himax-hx8379c-amazon-rook.c | 418 ++++++++++++++++++ 3 files changed, 428 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-himax-hx8379c-amazon-rook.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index d592f4f4b939a9..86dd71df087833 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -174,6 +174,15 @@ config DRM_PANEL_HIMAX_HX8279 7.0" 1200x1920 IPS LCD panel that uses a MIPI-DSI interface and others. +config DRM_PANEL_HIMAX_HX8379C_ROOK + tristate "Himax HX8379C-based panels" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y if you want to enable support for panels based on the + Himax HX8379C controller. + config DRM_PANEL_HIMAX_HX83102 tristate "Himax HX83102-based panels" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index a4291dc3905bed..69bbda43762dc0 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) += panel-feixin-k101-im2ba02.o obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX8279) += panel-himax-hx8279.o +obj-$(CONFIG_DRM_PANEL_HIMAX_HX8379C_ROOK) += panel-himax-hx8379c-amazon-rook.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX83102) += panel-himax-hx83102.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112A) += panel-himax-hx83112a.o obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112B) += panel-himax-hx83112b.o diff --git a/drivers/gpu/drm/panel/panel-himax-hx8379c-amazon-rook.c b/drivers/gpu/drm/panel/panel-himax-hx8379c-amazon-rook.c new file mode 100644 index 00000000000000..145c495312787f --- /dev/null +++ b/drivers/gpu/drm/panel/panel-himax-hx8379c-amazon-rook.c @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025-2026 Ben Grisdale + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define PANEL_INX 0 +#define PANEL_TIANMA 1 +#define PANEL_BOE 2 +#define PANEL_INXE 3 + +/* TODO */ +#define SKIP_PANEL_INIT + +struct rook_hx8379c_info { + const struct drm_display_mode *mode; + unsigned long mode_flags; + void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx); +}; + +struct rook_hx8379c { + struct drm_panel panel; + const struct rook_hx8379c_info *info; + struct mipi_dsi_device *dsi; + struct regulator_bulk_data *supplies; + struct gpio_desc *id0_gpio; + struct gpio_desc *id1_gpio; + struct gpio_desc *reset_gpio; +}; + +static const struct regulator_bulk_data rook_hx8379c_supplies[] = { + { .supply = "vcn" }, + { .supply = "vmch" }, + { .supply = "v1p8" }, + { .supply = "v3p3" }, +}; + +static inline +struct rook_hx8379c *to_rook_hx8379c(struct drm_panel *panel) +{ + return container_of(panel, struct rook_hx8379c, panel); +} + +#ifndef SKIP_PANEL_INIT +static void rook_hx8379c_reset(struct rook_hx8379c *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(1000, 2000); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + usleep_range(1000, 2000); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(5000, 6000); +} +#endif + +static int rook_hx8379c_unprepare(struct drm_panel *panel) +{ + struct rook_hx8379c *ctx = to_rook_hx8379c(panel); + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + ctx->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + +#ifndef SKIP_PANEL_INIT + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + usleep_range(5000, 6000); + + regulator_bulk_disable(ARRAY_SIZE(rook_hx8379c_supplies), + ctx->supplies); +#endif + + return dsi_ctx.accum_err; +} + +static int rook_hx8379c_prepare(struct drm_panel *panel) +{ + struct rook_hx8379c *ctx = to_rook_hx8379c(panel); + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; +#ifndef SKIP_PANEL_INIT + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(rook_hx8379c_supplies), + ctx->supplies); + if (ret < 0) { + dev_err(panel->dev, "Failed to enable regulators\n"); + return ret; + } + + /* Reset the panel ready for initialization in enable */ + rook_hx8379c_reset(ctx); +#endif + + ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM; + +#ifndef SKIP_PANEL_INIT + /* Perform the panel-specific init sequence. */ + ctx->info->init_sequence(&dsi_ctx); +#endif + + return dsi_ctx.accum_err; +} + +static int rook_hx8379c_enable(struct drm_panel *panel) +{ + struct rook_hx8379c *ctx = to_rook_hx8379c(panel); + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); + +#ifndef SKIP_PANEL_INIT + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 20); +#endif + + return dsi_ctx.accum_err; +} + +static int rook_hx8379c_disable(struct drm_panel *panel) +{ + struct rook_hx8379c *ctx = to_rook_hx8379c(panel); + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + +#ifndef SKIP_PANEL_INIT + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 20); +#endif + + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); + + return dsi_ctx.accum_err; +} + +static int rook_hx8379c_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct rook_hx8379c *ctx = to_rook_hx8379c(panel); + + return drm_connector_helper_get_modes_fixed(connector, ctx->info->mode); +} + +static const struct drm_display_mode rook_hx8379c_inx_mode = { + .clock = 26166, + .hdisplay = 480, + .hsync_start = 480 + 160, + .hsync_end = 480 + 160 + 100, + .htotal = 480 + 160 + 100 + 100, + .vdisplay = 480, + .vsync_start = 480 + 108, + .vsync_end = 480 + 108 + 3, + .vtotal = 480 + 108 + 3 + 12, + .width_mm = 79, /* 78.74 mm */ + .height_mm = 79, /* 78.74 mm */ + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static void rook_hx8379c_inx_init(struct mipi_dsi_multi_context *dsi_ctx) +{ + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb9, 0xff, 0x83, 0x79); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb1, 0x44, 0x18, 0x18, 0x31, 0x31, 0x50, 0xd0, 0xf2, 0x9e, 0x80, 0x38, 0x38, 0xf8, 0x33, 0x32, 0x22); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb2, 0x80, 0x14, 0x0f, 0x0a, 0x00, 0xb7, 0x11, 0x42, 0x1d); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb4, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0x10, 0xea, 0x1c, 0xea); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc7, 0x00, 0x00, 0x00, 0xc0); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xcc, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd2, 0x33); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd3, 0x00, 0x00, 0x00, 0x3c, 0x01, 0x14, 0x14, 0x32, 0x10, 0x03, 0x00, 0x03, 0x01, 0xf1, 0x01, 0xf1, 0x01, 0xf4, 0x01, 0xf4, 0x49, 0x44, 0x05, 0x05, 0x47, 0x05, 0x05, 0x47, 0x0d); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd5, 0x20, 0x21, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x1a, 0x1a, 0x1b, 0x1b, 0x18, 0x18, 0x28, 0x29, 0x24, 0x25, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd6, 0x25, 0x24, 0x03, 0x02, 0x01, 0x00, 0x07, 0x06, 0x05, 0x04, 0x1a, 0x1a, 0x1b, 0x1b, 0x18, 0x18, 0x29, 0x28, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe0, 0x00, 0x09, 0x0e, 0x2d, 0x33, 0x3f, 0x19, 0x39, 0x06, 0x0a, 0x0c, 0x17, 0x0d, 0x11, 0x13, 0x11, 0x13, 0x07, 0x12, 0x13, 0x18, 0x00, 0x08, 0x0d, 0x2d, 0x32, 0x3f, 0x19, 0x39, 0x06, 0x0a, 0x0c, 0x17, 0x0e, 0x10, 0x13, 0x11, 0x14, 0x08, 0x12, 0x14, 0x17); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbd, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc1, 0x01, 0x00, 0x08, 0x10, 0x18, 0x21, 0x27, 0x2f, 0x37, 0x3f, 0x47, 0x4f, 0x56, 0x5d, 0x65, 0x6d, 0x76, 0x7e, 0x86, 0x8e, 0x96, 0x9e, 0xa6, 0xaf, 0xb7, 0xbf, 0xc7, 0xcf, 0xd7, 0xdf, 0xe7, 0xef, 0xf7, 0xff, 0x01, 0x72, 0xf6, 0xed, 0x95, 0x60, 0x15, 0x01, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbd, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc1, 0x00, 0x08, 0x10, 0x17, 0x1f, 0x27, 0x2e, 0x36, 0x3f, 0x47, 0x4f, 0x56, 0x5d, 0x65, 0x6d, 0x76, 0x7e, 0x86, 0x8e, 0x96, 0x9e, 0xa6, 0xae, 0xb6, 0xbe, 0xc6, 0xce, 0xd6, 0xde, 0xe5, 0xed, 0xf5, 0xfc, 0x00, 0x4a, 0x51, 0xde, 0x91, 0x5b, 0xba, 0x3a, 0xc0); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbd, 0x02); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc1, 0x00, 0x08, 0x10, 0x15, 0x1e, 0x26, 0x2e, 0x36, 0x40, 0x48, 0x50, 0x57, 0x5f, 0x67, 0x6f, 0x78, 0x80, 0x88, 0x90, 0x99, 0xa1, 0xa9, 0xb2, 0xba, 0xc2, 0xca, 0xd2, 0xda, 0xe1, 0xe9, 0xf1, 0xf8, 0xff, 0x00, 0xab, 0x02, 0x0f, 0xec, 0x60, 0x64, 0xe7, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb6, 0x78, 0x78); +} + +static const struct drm_display_mode rook_hx8379c_tianma_mode = { + .clock = 22833, + .hdisplay = 480, + .hsync_start = 480 + 180, + .hsync_end = 480 + 180 + 100, + .htotal = 480 + 180 + 100 + 100, + .vdisplay = 480, + .vsync_start = 480 + 6, + .vsync_end = 480 + 6 + 4, + .vtotal = 480 + 6 + 4 + 7, + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static void rook_hx8379c_tianma_init(struct mipi_dsi_multi_context *dsi_ctx) +{ + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb9, 0xff, 0x83, 0x79); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb1, 0x44, 0x1a, 0x1a, 0x30, 0x30, 0x50, 0xd0, 0xe4, 0x54, 0x80, 0x38, 0x38, 0xf8, 0x22, 0x22, 0x22); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb2, 0x80, 0x14, 0x0b, 0x04, 0x10, 0x50, 0x11, 0x42, 0x1d); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb4, 0x01, 0xaa, 0x01, 0xaa, 0x01, 0xaa, 0x10, 0xea, 0x1c, 0xea); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc7, 0x00, 0x00, 0x00, 0xc0); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xcc, 0x02); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd2, 0x55); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd3, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x04, 0x32, 0x10, 0x03, 0x00, 0x03, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x17, 0x11, 0x08, 0x08, 0x13, 0x05, 0x05, 0x13, 0x09); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd5, 0x18, 0x18, 0x18, 0x18, 0x25, 0x24, 0x18, 0x18, 0x03, 0x02, 0x18, 0x18, 0x01, 0x00, 0x18, 0x18, 0x19, 0x19, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd6, 0x18, 0x18, 0x18, 0x18, 0x24, 0x25, 0x18, 0x18, 0x00, 0x01, 0x18, 0x18, 0x02, 0x03, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x18, 0x18, 0x20, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe0, 0x00, 0x0e, 0x15, 0x30, 0x32, 0x38, 0x27, 0x44, 0x07, 0x0b, 0x0d, 0x17, 0x0f, 0x12, 0x15, 0x14, 0x15, 0x08, 0x13, 0x15, 0x19, 0x00, 0x0e, 0x15, 0x30, 0x32, 0x38, 0x27, 0x44, 0x07, 0x0b, 0x0d, 0x17, 0x0f, 0x12, 0x15, 0x14, 0x15, 0x08, 0x13, 0x15, 0x19); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb6, 0x37, 0x3f); +} + +static const struct drm_display_mode rook_hx8379c_boe_mode = { + .clock = 22833, + .hdisplay = 480, + .hsync_start = 480 + 180, + .hsync_end = 480 + 180 + 100, + .htotal = 480 + 180 + 100 + 100, + .vdisplay = 480, + .vsync_start = 480 + 5, + .vsync_end = 480 + 5 + 4, + .vtotal = 480 + 5 + 4 + 8, + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static void rook_hx8379c_boe_init(struct mipi_dsi_multi_context *dsi_ctx) +{ + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb9, 0xff, 0x83, 0x79); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb1, 0x44, 0x1c, 0x1c, 0x37, 0x57, 0x90, 0xd0, 0xe2, 0x58, 0x80, 0x38, 0x38, 0xf8, 0x33, 0x34, 0x42); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb2, 0x80, 0x14, 0x0c, 0x30, 0x20, 0x50, 0x11, 0x42, 0x1d); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb4, 0x01, 0xaa, 0x01, 0xaf, 0x01, 0xaf, 0x10, 0xea, 0x1c, 0xea); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc7, 0x00, 0x00, 0x00, 0xc0); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xcc, 0x02); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd2, 0x77); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd3, 0x00, 0x07, 0x00, 0x00, 0x00, 0x08, 0x08, 0x32, 0x10, 0x01, 0x00, 0x01, 0x03, 0x72, 0x03, 0x72, 0x00, 0x08, 0x00, 0x08, 0x33, 0x33, 0x05, 0x05, 0x37, 0x05, 0x05, 0x37, 0x0a, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x01, 0x00, 0x0e); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x01, 0x00, 0x03, 0x02, 0x05, 0x04, 0x07, 0x06, 0x23, 0x22, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd6, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x18, 0x18, 0x19, 0x19, 0x18, 0x18, 0x06, 0x07, 0x04, 0x05, 0x02, 0x03, 0x00, 0x01, 0x20, 0x21, 0x22, 0x23, 0x18, 0x18, 0x18, 0x18); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe0, 0x00, 0x16, 0x1b, 0x30, 0x36, 0x3f, 0x23, 0x3f, 0x09, 0x0d, 0x0f, 0x18, 0x0e, 0x11, 0x13, 0x11, 0x14, 0x07, 0x12, 0x13, 0x18, 0x00, 0x17, 0x1c, 0x30, 0x36, 0x3f, 0x23, 0x40, 0x09, 0x0c, 0x0f, 0x18, 0x0e, 0x11, 0x13, 0x11, 0x12, 0x07, 0x12, 0x14, 0x18); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb6, 0x2c, 0x2c, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbd, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc1, 0x01, 0x00, 0x07, 0x10, 0x18, 0x21, 0x29, 0x31, 0x39, 0x42, 0x49, 0x51, 0x5a, 0x61, 0x6a, 0x72, 0x7b, 0x83, 0x8b, 0x93, 0x9b, 0xa3, 0xab, 0xb3, 0xba, 0xc1, 0xc9, 0xd3, 0xda, 0xe4, 0xea, 0xf2, 0xf9, 0xfe, 0x36, 0x07, 0x1c, 0xc0, 0x1b, 0x01, 0xf1, 0x34, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbd, 0x01); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc1, 0x00, 0x08, 0x11, 0x19, 0x22, 0x2a, 0x32, 0x3b, 0x43, 0x4a, 0x53, 0x5b, 0x63, 0x6b, 0x73, 0x7b, 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbb, 0xc2, 0xcb, 0xd3, 0xdb, 0xe5, 0xeb, 0xf3, 0xf9, 0xff, 0x3b, 0x1a, 0xb6, 0xa0, 0x07, 0x45, 0xc5, 0x37, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbd, 0x02); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc1, 0x00, 0x08, 0x10, 0x19, 0x22, 0x29, 0x32, 0x3b, 0x43, 0x4b, 0x54, 0x5c, 0x65, 0x6b, 0x72, 0x7c, 0x83, 0x8b, 0x93, 0x9b, 0xa3, 0xab, 0xb3, 0xba, 0xc2, 0xca, 0xd2, 0xda, 0xe2, 0xeb, 0xf1, 0xf8, 0xfd, 0x0c, 0x31, 0x83, 0x3c, 0x5b, 0x56, 0x1e, 0x5a, 0x00); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbd, 0x00); +} + +static const struct rook_hx8379c_info rook_hx8379c_inx_info = { + .mode = &rook_hx8379c_inx_mode, + .init_sequence = rook_hx8379c_inx_init, + .mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_CLOCK_NON_CONTINUOUS | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, +}; + +static const struct rook_hx8379c_info rook_hx8379c_tianma_info = { + .mode = &rook_hx8379c_tianma_mode, + .init_sequence = rook_hx8379c_tianma_init, + .mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, +}; + +static const struct rook_hx8379c_info rook_hx8379c_boe_info = { + .mode = &rook_hx8379c_boe_mode, + .init_sequence = rook_hx8379c_boe_init, + .mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, +}; + +static const struct rook_hx8379c_info* +rook_hx8379c_get_panel_info(struct rook_hx8379c *ctx) +{ + int id0, id1, id; + + id0 = gpiod_get_value_cansleep(ctx->id0_gpio); + id1 = gpiod_get_value_cansleep(ctx->id1_gpio); + + id = (id1 << 1) | id0; + + pr_err("%s: Panel ID: %d", __func__, id0); + + switch (id) { + case PANEL_INX: + case PANEL_INXE: + return &rook_hx8379c_inx_info; + case PANEL_TIANMA: + return &rook_hx8379c_tianma_info; + case PANEL_BOE: + return &rook_hx8379c_boe_info; + default: + return ERR_PTR(-EINVAL); + } +} + +static const struct drm_panel_funcs rook_hx8379c_panel_funcs = { + .prepare = rook_hx8379c_prepare, + .unprepare = rook_hx8379c_unprepare, + .enable = rook_hx8379c_enable, + .disable = rook_hx8379c_disable, + .get_modes = rook_hx8379c_get_modes, +}; + +static int rook_hx8379c_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct rook_hx8379c *ctx; + int ret; + + ctx = devm_drm_panel_alloc(&dsi->dev, struct rook_hx8379c, panel, + &rook_hx8379c_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + if (IS_ERR(ctx)) + return PTR_ERR(ctx); + + ctx->panel.prepare_prev_first = true; + + mipi_dsi_set_drvdata(dsi, ctx); + ctx->dsi = dsi; + + ret = devm_regulator_bulk_get_const(dev, + ARRAY_SIZE(rook_hx8379c_supplies), + rook_hx8379c_supplies, + &ctx->supplies); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get regulators\n"); + +#ifdef SKIP_PANEL_INIT + ret = regulator_bulk_enable(ARRAY_SIZE(rook_hx8379c_supplies), + ctx->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators\n"); + return ret; + } +#endif + + ctx->id0_gpio = devm_gpiod_get(dev, "id0", GPIOD_IN); + if (IS_ERR(ctx->id0_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->id0_gpio), + "Failed to get ID0 GPIO\n"); + + ctx->id1_gpio = devm_gpiod_get(dev, "id1", GPIOD_IN); + if (IS_ERR(ctx->id1_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->id1_gpio), + "Failed to get ID1 GPIO\n"); + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->id1_gpio), + "Failed to get Reset GPIO\n"); + + ctx->info = rook_hx8379c_get_panel_info(ctx); + if (IS_ERR(ctx->info)) + return dev_err_probe(dev, PTR_ERR(ctx->info), + "Failed to read panel ID\n"); + + ret = drm_panel_of_backlight(&ctx->panel); + if (ret) + return dev_err_probe(dev, ret, "Failed to get backlight\n"); + + drm_panel_add(&ctx->panel); + + dsi->mode_flags = ctx->info->mode_flags; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->lanes = 2; + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + drm_panel_remove(&ctx->panel); + return dev_err_probe(dev, ret, "Failed to attach to DSI host\n"); + } + + return 0; +} + +static void rook_hx8379c_remove(struct mipi_dsi_device *dsi) +{ + struct rook_hx8379c *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + ret = mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret); + + drm_panel_remove(&ctx->panel); +} + +static const struct of_device_id rook_hx8379c_of_match[] = { + { .compatible = "amazon,rook-hx8379c" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rook_hx8379c_of_match); + +static struct mipi_dsi_driver rook_hx8379c_driver = { + .probe = rook_hx8379c_probe, + .remove = rook_hx8379c_remove, + .driver = { + .name = "panel-amazon-rook-hx8379c", + .of_match_table = rook_hx8379c_of_match, + }, +}; +module_mipi_dsi_driver(rook_hx8379c_driver); + +MODULE_AUTHOR("Ben Grisdale "); +MODULE_DESCRIPTION("DRM Driver for Rook's HX8379c Panels"); +MODULE_LICENSE("GPL v2"); From 68c6f5c181170c92a6c603a6241757e3c0f4f15a Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 22:41:45 +0000 Subject: [PATCH 109/126] arm64: dts: mediatek: mt8163-amazon: Add display backlight node Add a display backlight node for all Amazon MT8163 devices, since they all use the display PWM based backlight control for the display. Signed-off-by: bengris32 --- .../boot/dts/mediatek/mt8163-amazon-common.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi index d9929dd78b1b71..33083e37796089 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-common.dtsi @@ -15,6 +15,14 @@ stdout-path = "serial0:921600n8"; }; + disp_backlight: display-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 500000>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <512>; + }; + memory { device_type = "memory"; reg = <0 0x40000000 0 0x20000000>; @@ -140,6 +148,10 @@ interrupts-extended = <&pio 24 IRQ_TYPE_LEVEL_HIGH>; }; +&pwm0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_default>; From d627f5a6124e644b283fd4cf5ca39f70133c99de Mon Sep 17 00:00:00 2001 From: bengris32 Date: Sun, 14 Dec 2025 19:28:39 +0000 Subject: [PATCH 110/126] arm64: dts: mediatek: mt8163-amazon-rook: Enable display Signed-off-by: bengris32 --- .../boot/dts/mediatek/mt8163-amazon-rook.dts | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts index 5d5798e7e0e3ee..c3bbb6c87bc5bc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts @@ -37,6 +37,30 @@ }; }; + disp_v1p8: regulator-disp-v1p8 { + compatible = "regulator-fixed"; + pinctrl-0 = <&disp_v1p8_pins_default>; + pinctrl-names = "default"; + regulator-name = "disp-v1p8"; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 85 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + disp_v3p3: regulator-disp-v3p3 { + compatible = "regulator-fixed"; + pinctrl-0 = <&disp_v3p3_pins_default>; + pinctrl-names = "default"; + regulator-name = "disp-v3p3"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 125 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + rfkill { compatible = "rfkill-gpio"; pinctrl-names = "default"; @@ -47,6 +71,50 @@ }; }; +&dsi { + /delete-property/ resets; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + panel: panel@0 { + compatible = "amazon,rook-hx8379c"; + reg = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcm_pins_default>; + + backlight = <&disp_backlight>; + + id0-gpios = <&pio 32 GPIO_ACTIVE_HIGH>; + id1-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 83 GPIO_ACTIVE_LOW>; + + vcn-supply = <&mt6323_vcn33_wifi_reg>; + vmch-supply = <&mt6323_vmch_reg>; + v1p8-supply = <&disp_v1p8>; + v3p3-supply = <&disp_v3p3>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port { + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + &i2c0 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -68,11 +136,24 @@ }; }; +&mipi_tx0 { + /delete-property/ resets; + status = "okay"; +}; + +&mt6323_vcn33_wifi_reg { + regulator-boot-on; +}; + &mt6323_vibr_reg { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; +&mt6323_vmch_reg { + regulator-boot-on; +}; + &mt6323_vusb_reg { regulator-always-on; }; @@ -111,6 +192,30 @@ }; }; + disp_v1p8_pins_default: disp-v1p8-pins { + pins { + pinmux = ; + }; + }; + + disp_v3p3_pins_default: disp-v3p3-pins { + pins { + pinmux = ; + }; + }; + + lcm_pins_default: lcm-pins { + pins-id { + pinmux = , + ; + input-enable; + }; + + pins-reset { + pinmux = ; + }; + }; + touch_pins: touch-pins { pins-irq { pinmux = ; From 5fe31e3925e2caa9078d690cccbe4a8f579d90a7 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sun, 22 Feb 2026 20:26:39 +0000 Subject: [PATCH 111/126] [HACK] arm64: dts: mediatek: mt8163-amazon-rook: Keep display regs on Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts index c3bbb6c87bc5bc..bcac64b3202eac 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-rook.dts @@ -43,6 +43,7 @@ pinctrl-names = "default"; regulator-name = "disp-v1p8"; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&pio 85 GPIO_ACTIVE_HIGH>; @@ -55,6 +56,7 @@ pinctrl-names = "default"; regulator-name = "disp-v3p3"; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&pio 125 GPIO_ACTIVE_HIGH>; @@ -143,6 +145,7 @@ &mt6323_vcn33_wifi_reg { regulator-boot-on; + regulator-always-on; }; &mt6323_vibr_reg { @@ -152,6 +155,7 @@ &mt6323_vmch_reg { regulator-boot-on; + regulator-always-on; }; &mt6323_vusb_reg { From f3e82581b4a24a2f09daf3ca8f601cf8b98b6d2b Mon Sep 17 00:00:00 2001 From: Jack Matthews Date: Wed, 25 Feb 2026 17:03:23 -0500 Subject: [PATCH 112/126] arm64: dts: mediatek: mt8163-amazon-show: Enable USB Co-authored-by: Jack Matthews Signed-off-by: Ben Grisdale Signed-off-by: Jack Matthews --- .../boot/dts/mediatek/mt8163-amazon-show.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi index a57980d70375d6..17d25668389bc4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi @@ -5,3 +5,17 @@ */ #include "mt8163-amazon-common.dtsi" + +&mt6323_vusb_reg { + regulator-always-on; +}; + +&u2phy0 { + status = "okay"; +}; + +&usb0 { + /* No 5V supply for OTG support. */ + dr_mode = "peripheral"; + status = "okay"; +}; From b283332b161f9b86deea80a186488cdda6ce81a3 Mon Sep 17 00:00:00 2001 From: Ben Grisdale Date: Sat, 13 Dec 2025 13:06:18 +0000 Subject: [PATCH 113/126] arm64: dts: mediatek: mt8163-amazon-crown: Set version property Signed-off-by: Jack Matthews Signed-off-by: Ben Grisdale --- arch/arm64/boot/dts/mediatek/mt8163-amazon-crown.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-crown.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-crown.dts index 0dd104cd527df7..8e09d948b77c8b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-crown.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-crown.dts @@ -11,4 +11,7 @@ model = "Amazon Echo Show 8 (2019)"; compatible = "amazon,crown", "mediatek,mt8163"; chassis-type = "embedded"; + + /* Needed by stock bootloader */ + version = "pvt"; }; From 07038f38b108b991a38cf4c9d4d567a054cef303 Mon Sep 17 00:00:00 2001 From: Jack Matthews Date: Wed, 25 Feb 2026 17:07:08 -0500 Subject: [PATCH 114/126] arm64: dts: mediatek: mt8163-amazon-checkers: Set version property Signed-off-by: Jack Matthews --- arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts index 786a2827256d01..870d85d9a48e74 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts @@ -11,4 +11,7 @@ model = "Amazon Echo Show 5 (2019)"; compatible = "amazon,checkers", "mediatek,mt8163"; chassis-type = "embedded"; + + /* Needed by stock bootloader */ + version = "dvt"; }; From 86bd7600aa89b4a7c939b28e8a47cdacf10aba3e Mon Sep 17 00:00:00 2001 From: Jack Matthews Date: Wed, 25 Feb 2026 17:07:22 -0500 Subject: [PATCH 115/126] arm64: dts: mediatek: mt8163-amazon-cronos: Set version property Signed-off-by: Jack Matthews --- arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.1.dts | 3 +++ arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.2.dts | 3 +++ arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.3.dts | 3 +++ arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dts | 3 +++ 4 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.1.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.1.dts index cdde96e608818e..0cb1dd70f5aba0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.1.dts @@ -11,4 +11,7 @@ model = "Amazon Echo Show 5 (2021) (v4.1)"; compatible = "amazon,cronos-v4.1", "amazon,cronos", "mediatek,mt8163"; chassis-type = "embedded"; + + /* Needed by stock bootloader */ + version = "pvt_4_1"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.2.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.2.dts index 5882cf6abe9126..b52aa979e01622 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.2.dts @@ -11,4 +11,7 @@ model = "Amazon Echo Show 5 (2021) (v4.2)"; compatible = "amazon,cronos-v4.2", "amazon,cronos", "mediatek,mt8163"; chassis-type = "embedded"; + + /* Needed by stock bootloader */ + version = "pvt_4_2"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.3.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.3.dts index cb96ffe29b02a9..ca906a54f210f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.3.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos-v4.3.dts @@ -11,4 +11,7 @@ model = "Amazon Echo Show 5 (2021) (v4.3)"; compatible = "amazon,cronos-v4.3", "amazon,cronos", "mediatek,mt8163"; chassis-type = "embedded"; + + /* Needed by stock bootloader */ + version = "pvt_4_3"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dts index 1393630b4b1754..3eb3a939eb5b59 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-cronos.dts @@ -11,4 +11,7 @@ model = "Amazon Echo Show 5 (2021)"; compatible = "amazon,cronos", "mediatek,mt8163"; chassis-type = "embedded"; + + /* Needed by stock bootloader */ + version = "pvt"; }; From d9ed9a7fb9321ad3694144df0a705c8bbe02e12a Mon Sep 17 00:00:00 2001 From: Jack Matthews Date: Wed, 25 Feb 2026 17:47:53 -0500 Subject: [PATCH 116/126] arm64: dts: mediatek: mt8163-amazon-show: Add GPIO keys Signed-off-by: Jack Matthews Signed-off-by: Ben Grisdale --- .../boot/dts/mediatek/mt8163-amazon-show.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi index 17d25668389bc4..c7a5b5554b1854 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi @@ -4,8 +4,40 @@ * Copyright (c) 2025-2026 Jack Matthews */ +#include +#include + #include "mt8163-amazon-common.dtsi" +/ { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pio 36 GPIO_ACTIVE_LOW>; + debounce-interval = <20>; + }; + + key-volume-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pio 37 GPIO_ACTIVE_LOW>; + debounce-interval = <20>; + }; + + switch-camera-lens-cover { + label = "Camera Lens Cover"; + linux,input-type = ; + linux,code = ; + gpios = <&pio 142 GPIO_ACTIVE_LOW>; + }; + }; +}; + &mt6323_vusb_reg { regulator-always-on; }; @@ -19,3 +51,15 @@ dr_mode = "peripheral"; status = "okay"; }; + +&pio { + gpio_keys_pins: gpio-keys-pins { + pins { + pinmux = , + , + ; + bias-pull-up; + input-enable; + }; + }; +}; From ab5f99105bb003cbd5ea33c4097e92528bb450cf Mon Sep 17 00:00:00 2001 From: Jack Matthews Date: Thu, 26 Feb 2026 14:56:58 -0500 Subject: [PATCH 117/126] dt-bindings: vendor-prefixes: Add Solteam Add Solteam Electronics Co, Ltd. https://www.solteam.com.tw/ https://www.solteam-medical.com/ https://www.solteamopto.com.tw/ Signed-off-by: Jack Matthews --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 28784d66ae7ba5..ef26ab265a7468 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1553,6 +1553,8 @@ patternProperties: description: SolidRun "^solomon,.*": description: Solomon Systech Limited + "^solteam,.*": + description: Solteam Electronics Co, Ltd. "^somfy,.*": description: Somfy Systems Inc. "^sony,.*": From e59744cfd430a0476c77ca53eef724fb23e911ac Mon Sep 17 00:00:00 2001 From: Jack Matthews Date: Thu, 26 Feb 2026 15:02:48 -0500 Subject: [PATCH 118/126] iio: light: Add DT bindings for JSA1212 This adds device tree bindings for the JSA1212/JSA1214 light and proximity sensor. Signed-off-by: Jack Matthews --- .../bindings/iio/light/solteam,jsa1212.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/light/solteam,jsa1212.yaml diff --git a/Documentation/devicetree/bindings/iio/light/solteam,jsa1212.yaml b/Documentation/devicetree/bindings/iio/light/solteam,jsa1212.yaml new file mode 100644 index 00000000000000..a4682e35907088 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/solteam,jsa1212.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/solteam,jsa1212.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Solteam Opto JSA1212 I2C Proximity and Light sensor + +maintainers: + - Jack Matthews + +allOf: + - $ref: ../common.yaml# + +properties: + compatible: + enum: + - solteam,jsa1212 + - solteam,jsa1214 + + reg: + maxItems: 1 + + vdd-supply: true + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@44 { + compatible = "solteam,jsa1212"; + reg = <0x44>; + + vdd-supply = <&mt6323_vcn28_reg>; + }; + }; From b050d9fda73bbaea77eaf411622f66d2f0c98b5d Mon Sep 17 00:00:00 2001 From: Jack Matthews Date: Thu, 26 Feb 2026 05:22:41 -0500 Subject: [PATCH 119/126] iio: jsa1212: Add support for JSA1214 Adds support for the JSA1214 ambient light sensor. This sensor lacks proximity compared to JSA1212. Signed-off-by: Jack Matthews --- drivers/iio/light/jsa1212.c | 97 ++++++++++++++++++++++++++++++------- 1 file changed, 79 insertions(+), 18 deletions(-) diff --git a/drivers/iio/light/jsa1212.c b/drivers/iio/light/jsa1212.c index 6978d02a4df592..9d4f2664958463 100644 --- a/drivers/iio/light/jsa1212.c +++ b/drivers/iio/light/jsa1212.c @@ -17,10 +17,13 @@ #include #include #include +#include + #include #include /* JSA1212 reg address */ +#define JSA1212_ID_REG 0x00 #define JSA1212_CONF_REG 0x01 #define JSA1212_INT_REG 0x02 #define JSA1212_PXS_LT_REG 0x03 @@ -112,15 +115,28 @@ enum jsa1212_op_mode { JSA1212_OPMODE_PXS_EN, }; +enum { + jsa1212 = 0, + jsa1214, +}; + struct jsa1212_data { struct i2c_client *client; struct mutex lock; + const struct jsa1212_chip_info *chip_info; u8 als_rng_idx; bool als_en; /* ALS enable status */ bool pxs_en; /* proximity enable status */ struct regmap *regmap; }; +struct jsa1212_chip_info { + const char *name; + u8 chipid; + const struct iio_chan_spec *channels; + int num_channels; +}; + /* ALS range idx to val mapping */ static const int jsa1212_als_range_val[] = {2048, 1024, 512, 256, 128, 128, 128, 128}; @@ -261,10 +277,33 @@ static const struct iio_chan_spec jsa1212_channels[] = { } }; +static const struct iio_chan_spec jsa1214_channels[] = { + { + .type = IIO_LIGHT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + } +}; + static const struct iio_info jsa1212_info = { .read_raw = &jsa1212_read_raw, }; +static const struct jsa1212_chip_info jsa1212_chip_info_tbl[] = { + [jsa1212] = { + .name = JSA1212_DRIVER_NAME, + .chipid = 0x00, + .channels = jsa1212_channels, + .num_channels = ARRAY_SIZE(jsa1212_channels), + }, + [jsa1214] = { + .name = "jsa1214", + .chipid = 0x21, + .channels = jsa1214_channels, + .num_channels = ARRAY_SIZE(jsa1214_channels), + }, +}; + static int jsa1212_chip_init(struct jsa1212_data *data) { int ret; @@ -311,34 +350,47 @@ static int jsa1212_probe(struct i2c_client *client) { struct jsa1212_data *data; struct iio_dev *indio_dev; - struct regmap *regmap; - int ret; + int chipid_raw, ret; indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); if (!indio_dev) return -ENOMEM; - regmap = devm_regmap_init_i2c(client, &jsa1212_regmap_config); - if (IS_ERR(regmap)) { - dev_err(&client->dev, "Regmap initialization failed.\n"); - return PTR_ERR(regmap); - } - data = iio_priv(indio_dev); - - i2c_set_clientdata(client, indio_dev); data->client = client; - data->regmap = regmap; + + data->regmap = devm_regmap_init_i2c(client, &jsa1212_regmap_config); + if (IS_ERR(data->regmap)) + return PTR_ERR(data->regmap); + + data->chip_info = i2c_get_match_data(client); + if (!data->chip_info) + return dev_err_probe(&client->dev, -ENODEV, "Could not find matching chip data\n"); mutex_init(&data->lock); - ret = jsa1212_chip_init(data); + ret = devm_regulator_get_enable_optional(&client->dev, "vdd"); + if (ret < 0 && ret != -ENODEV) + return dev_err_probe(&client->dev, ret, + "Failed to get regulator\n"); + + /* Verify Chip ID */ + ret = regmap_read(data->regmap, JSA1212_ID_REG, &chipid_raw); if (ret < 0) return ret; - indio_dev->channels = jsa1212_channels; - indio_dev->num_channels = ARRAY_SIZE(jsa1212_channels); - indio_dev->name = JSA1212_DRIVER_NAME; + if (chipid_raw != data->chip_info->chipid) { + dev_err(&client->dev, "ID mismatch: got 0x%x, expected 0x%x\n", + chipid_raw, data->chip_info->chipid); + return -ENODEV; + } + ret = jsa1212_chip_init(data); + if (ret < 0) + return dev_err_probe(&client->dev, ret, "chip init failed\n"); + + indio_dev->channels = data->chip_info->channels; + indio_dev->num_channels = data->chip_info->num_channels; + indio_dev->name = data->chip_info->name; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &jsa1212_info; @@ -422,22 +474,31 @@ static DEFINE_SIMPLE_DEV_PM_OPS(jsa1212_pm_ops, jsa1212_suspend, jsa1212_resume); static const struct acpi_device_id jsa1212_acpi_match[] = { - {"JSA1212", 0}, + {"JSA1212", (kernel_ulong_t)&jsa1212_chip_info_tbl[jsa1212] }, { } }; MODULE_DEVICE_TABLE(acpi, jsa1212_acpi_match); static const struct i2c_device_id jsa1212_id[] = { - { JSA1212_DRIVER_NAME }, + { JSA1212_DRIVER_NAME, (kernel_ulong_t)&jsa1212_chip_info_tbl[jsa1212] }, { } }; MODULE_DEVICE_TABLE(i2c, jsa1212_id); + +static const struct of_device_id jsa1212_of_match[] = { + { .compatible = "solteam,jsa1212", .data = &jsa1212_chip_info_tbl[jsa1212] }, + { .compatible = "solteam,jsa1214", .data = &jsa1212_chip_info_tbl[jsa1214] }, + { } +}; +MODULE_DEVICE_TABLE(of, jsa1212_of_match); + static struct i2c_driver jsa1212_driver = { .driver = { .name = JSA1212_DRIVER_NAME, .pm = pm_sleep_ptr(&jsa1212_pm_ops), - .acpi_match_table = jsa1212_acpi_match, + .acpi_match_table = ACPI_PTR(jsa1212_acpi_match), + .of_match_table = jsa1212_of_match, }, .probe = jsa1212_probe, .remove = jsa1212_remove, From c3a351f17a3133975abe324f88965ae864817149 Mon Sep 17 00:00:00 2001 From: Jack Matthews Date: Thu, 26 Feb 2026 05:23:44 -0500 Subject: [PATCH 120/126] arm64: dts: mediatek: mt8163-amazon-show: Add JSA1214 light sensor Signed-off-by: Jack Matthews --- .../boot/dts/mediatek/mt8163-amazon-show.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi index c7a5b5554b1854..155764b64c057e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-show.dtsi @@ -38,6 +38,20 @@ }; }; +&i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_default>; + status = "okay"; + + light-sensor@44 { + compatible = "solteam,jsa1214"; + reg = <0x44>; + + vdd-supply = <&mt6323_vcn28_reg>; + }; +}; + &mt6323_vusb_reg { regulator-always-on; }; @@ -62,4 +76,12 @@ input-enable; }; }; + + i2c0_pins_default: i2c0-pins { + pins { + pinmux = , + ; + bias-disable; + }; + }; }; From 07b2c1efa31c3d486eeca2d5da907f4b15cf5157 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Fri, 22 May 2026 21:46:42 +0900 Subject: [PATCH 121/126] arm64: dts: mt8163: add missing #cooling-cells Signed-off-by: Akari Tsuyukusa --- arch/arm64/boot/dts/mediatek/mt8163.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163.dtsi b/arch/arm64/boot/dts/mediatek/mt8163.dtsi index 83676d180f88e1..5d64b7750a41fd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -136,6 +137,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -156,6 +158,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -176,6 +179,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -196,6 +200,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + #cooling-cells = <2>; }; cpu-map { From 3122b263237e2c5ccf631bc4558107e9332ba6f3 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Fri, 22 May 2026 22:00:09 +0900 Subject: [PATCH 122/126] clk: mediatek: mt8163-apmixedsys: support refactor Link: https://github.com/torvalds/linux/commit/c9ced38af56fe6411118c6bc6522eab80849326d Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8163-apmixedsys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt8163-apmixedsys.c b/drivers/clk/mediatek/clk-mt8163-apmixedsys.c index 23e63c924bf079..43510160488525 100644 --- a/drivers/clk/mediatek/clk-mt8163-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8163-apmixedsys.c @@ -145,7 +145,7 @@ static int clk_mt8163_apmixed_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); if (ret) goto free_clk_data; From a9ce840556641e9ee321f0905daa0a22018b7fb8 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Fri, 22 May 2026 22:03:01 +0900 Subject: [PATCH 123/126] arm64: defconfig: add checkers_defconfig Signed-off-by: Akari Tsuyukusa --- arch/arm64/configs/checkers_defconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 arch/arm64/configs/checkers_defconfig diff --git a/arch/arm64/configs/checkers_defconfig b/arch/arm64/configs/checkers_defconfig new file mode 100644 index 00000000000000..bd991297bb2c64 --- /dev/null +++ b/arch/arm64/configs/checkers_defconfig @@ -0,0 +1,14 @@ +CONFIG_ARCH_MEDIATEK=y + +CONFIG_COMMON_CLK_MT8163=y +CONFIG_COMMON_CLK_MT8163_AUDSYS=y +CONFIG_COMMON_CLK_MT8163_IMGSYS=y +CONFIG_COMMON_CLK_MT8163_MFGCFG=y +CONFIG_COMMON_CLK_MT8163_MMSYS=y +CONFIG_COMMON_CLK_MT8163_VDECSYS=y +CONFIG_COMMON_CLK_MT8163_VENCSYS=y + +CONFIG_PINCTRL_MTK=y +CONFIG_PINCTRL_MT8163=y + +CONFIG_SND_SOC_MT8163=y From 8ba03fb989576137243b6a5ab8a7112019658974 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Fri, 22 May 2026 22:17:51 +0900 Subject: [PATCH 124/126] clk: mediatek: mt8196: Select REGMAP_MMIO for vlpckgen The MediaTek MT8196 vlpckgen clock driver uses __devm_regmap_init_mmio_clk() by devm_regmap_init_mmio(), which is defined in drivers/base/regmap/regmap-mmio.c. However, the driver's Kconfig entry does not select REGMAP_MMIO. This causes a linker error when REGMAP_MMIO is not enabled. Fix this by selecting REGMAP_MMIO in the Kconfig entry. Fixes: 2f8b3ae6f0cb ("clk: mediatek: Add MT8196 vlpckgen clock support") Cc: stable@vger.kernel.org Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 74584270755b5d..7ddbccb2e8e15e 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -1056,6 +1056,7 @@ config COMMON_CLK_MT8196 tristate "Clock driver for MediaTek MT8196" depends on ARM64 || COMPILE_TEST select COMMON_CLK_MEDIATEK + select REGMAP_MMIO default ARCH_MEDIATEK help This driver supports MediaTek MT8196 basic clocks. From 22c5a99b4a620efad8843c443808c483b8b1fa1a Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Fri, 22 May 2026 23:06:32 +0900 Subject: [PATCH 125/126] arm64: dts: mediatek: split amazon-checkers DT Downstream files are separated depending on the board version. - checkers_dvt.dts - checkers_evt.dts - checkers_hvt.dts - checkers_proto.dts - checkers_pvt.dts Link: https://github.com/amazon-oss/android_kernel_amazon_mt8163/tree/c374d6392fa0175064357b890d3041efd1390600/arch/arm64/boot/dts/mediatek Signed-off-by: Akari Tsuyukusa --- arch/arm64/boot/dts/mediatek/Makefile | 2 +- .../dts/mediatek/mt8163-amazon-checkers-dvt.dts | 14 ++++++++++++++ ...on-checkers.dts => mt8163-amazon-checkers.dtsi} | 4 ---- 3 files changed, 15 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers-dvt.dts rename arch/arm64/boot/dts/mediatek/{mt8163-amazon-checkers.dts => mt8163-amazon-checkers.dtsi} (84%) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 8ed8405accf9b6..2dc17321af703b 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -85,7 +85,7 @@ mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18-dtbs := \ mt7988a-bananapi-bpi-r4-pro-cn18.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-biscuit.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-checkers.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-checkers-dvt.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-cronos-v4.1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-cronos-v4.2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8163-amazon-cronos-v4.3.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers-dvt.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers-dvt.dts new file mode 100644 index 00000000000000..f10ac7521f23a1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers-dvt.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (c) 2025-2026 Ben Grisdale + * Copyright (c) 2025-2026 Jack Matthews + * Copyright (c) 2026 Akari Tsuyukusa + */ + +/dts-v1/; +#include "mt8163-amazon-checkers.dtsi" + +/ { + /* Needed by stock bootloader */ + version = "dvt"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts b/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dtsi similarity index 84% rename from arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts rename to arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dtsi index 870d85d9a48e74..ec88ffdf375ca2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dts +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dtsi @@ -4,14 +4,10 @@ * Copyright (c) 2025-2026 Jack Matthews */ -/dts-v1/; #include "mt8163-amazon-show.dtsi" / { model = "Amazon Echo Show 5 (2019)"; compatible = "amazon,checkers", "mediatek,mt8163"; chassis-type = "embedded"; - - /* Needed by stock bootloader */ - version = "dvt"; }; From e257041d9fadb5a7057e456c4ba6f592a7a424ec Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 24 May 2026 01:53:52 +0900 Subject: [PATCH 126/126] WIP: simple-framebuffer Signed-off-by: Akari Tsuyukusa --- .../dts/mediatek/mt8163-amazon-checkers.dtsi | 32 +++++++++++++++++++ arch/arm64/configs/checkers_defconfig | 19 +++++++++++ 2 files changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dtsi b/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dtsi index ec88ffdf375ca2..c6601cd990c6b4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8163-amazon-checkers.dtsi @@ -10,4 +10,36 @@ model = "Amazon Echo Show 5 (2019)"; compatible = "amazon,checkers", "mediatek,mt8163"; chassis-type = "embedded"; + + chosen { + bootargs = "console=tty0"; + + framebuffer { + compatible = "simple-framebuffer"; + memory-region = <&framebuffer_reserved>; + width = <480>; + height = <960>; + stride = <(480 * 4)>; + format = "a8b8g8r8"; + + status = "okay"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + ranges; + + framebuffer_reserved: memory@5f900000 { + reg = <0 0x5f900000 0 0x700000>; + }; + }; +}; + +&usb0 { + /* No 5V supply for OTG support. */ + dr_mode = "peripheral"; + status = "okay"; }; diff --git a/arch/arm64/configs/checkers_defconfig b/arch/arm64/configs/checkers_defconfig index bd991297bb2c64..0f07c1a720e955 100644 --- a/arch/arm64/configs/checkers_defconfig +++ b/arch/arm64/configs/checkers_defconfig @@ -12,3 +12,22 @@ CONFIG_PINCTRL_MTK=y CONFIG_PINCTRL_MT8163=y CONFIG_SND_SOC_MT8163=y + +CONFIG_WATCHDOG=y +CONFIG_MEDIATEK_WATCHDOG=y + +CONFIG_USB_GADGET=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_MEDIATEK=y +CONFIG_PHY_MTK_TPHY=y + +CONFIG_DRM=y +CONFIG_DRM_SIMPLEDRM=y +CONFIG_VT_CONSOLE=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y